Monte Carlo (MC) techniques are widely applied to check a design on its robustness and for estimating the production yield of integrated circuits. Using standard random MC and the sample yield for estimation, a very large number of samples is required for accurate verification, especially if a high yield is desired. This can make MC extremely time consuming, but if the data follows a normal Gaussian distribution a much faster yield prediction is possible by using the well-known CPKmethod. We extended this specification-distance-based scheme for the far more difficult general non-normal case by three different means, ending up in a new generalized process capability index named CGPK. First, we apply parametric modeling only to the specification-sided distribution part. This way any difficulties in distribution parts that actually have little yield impact do not degrade the model fit anymore. Second, to improve the parametric model we introduce a new tail parameter t. Third, to allow modeling of difficult asymmetrical, multimodal or flat distributions we also introduce a new reference location parameter instead of using the mean. An advantage of improving MC this way is that-in opposite to many other MC enhancements (like importance sampling)-the performance of the CGPKis not negatively impacted by design complexity. We described the formulation of the CGPKand derived confidence intervals using an advanced bootstrap scheme. We verified the performance against the sample yield and CPKfor a representative set of distributions, including real production data and MC data from the design of a CMOS operational amplifier and other circuits.

This paper presents two initiatives run by groups of engineering students at the University of Porto: the Microelectronics Students' Group and BioStar. These groups are student-led initiatives that promote different scientific fields through self-guided projects. Both experiences have proven to be very successful in increasing the undergraduate student's interest in science and technology. This work reports the activities, organization and main methodologies employed by these groups, which can be seen as successful approaches to enhance the technical curriculum of students.

This work addresses a built-in self-test methodology for circuit cell identification under specific matching conditions. The proposed technique is applied to the CMOS realization of a reduced-KII network, which is a system model of the biological olfactory cortex. This model behaves as an associative memory, a useful tool for information and adaptive processes. Based on a mixed-signal approach, the test strategy makes proper use of the circuits comprising the network structure, and provides self reconfiguration as well. Both testing procedures and design of essential building blocks are described in this paper. Simulation results are presented for a reduced-KII network comprising 128-cells, sequentially tested for matching in terms of offsets and their dynamic performances.