It is difficult to improve the single-thread performance of a processor in memory-intensive programs because processors have hit the memory wall, i.e., the large speed discrepancy between the processors and the main memory. Exploiting memory-level parallelism (MLP) is an effective way to overcome this problem. One scheme for exploiting MLP is aggressive out-of-order execution. To achieve this, large instruction window resources (i.e., the reorder buffer, the issue queue, and the load/store queue) are required; however, simply enlarging these resources degrades the clock cycle time. While pipelining these resources can solve this problem, this leads to instruction issue delays, which prevents instruction-level parallelism (ILP) from being exploited effectively. As a result, the performance of compute-intensive programs is degraded dramatically.

The tradeoff between complexity and attained instructions per cycle is often an important issue in microarchitectural designs. In this design phase, quick quantification of the complexity (i.e., delay) of relevant structures is required. The issue queue is one of such complex structures for which it is difficult to estimate delay. In this paper, we evaluate the issue queue delay to aid microarchitectural design. Our study includes two features: a circuit design and evaluation. First, we introduce banking the tag RAM, which is one of the components comprising the issue queue, to reduce the delay. Unlike normal RAM, banking the tag RAM is not straightforward, because of its uniqueness in the organization of the issue queue. Second, we explore and identify a correct critical path in the issue queue. A previous study summed the critical path of each component in the issue queue to obtain the delay of the issue queue, but this does not provide the correct delay of the issue queue, because the critical paths of each component are not connected logically. In the evaluation assuming 32nm LSI technology, we obtained the delays of an issue queue with eight to 128 entries. The process of banking the tag RAM and identifying the correct critical path reduces the delay by up to 20%, compared with not banking the tag RAM and simply summing the critical path delay of each component.