Delay faults have become increasingly important in modern designs due to decreasing technology node size and increasing operation frequency. However, diagnosis of delay faults can be challenging since there are typically few failing bits in the test failures. In this work, a two-phase flow is presented to identify systematic delay failures and improve their corresponding diagnosis resolution. First, the subset relationships among test failures are analyzed to identify systematic defects. Then, representative test failures in the subset relationships are selected to diagnose the defect behavior. Experiments on two cores of an industrial design with three cases show over 33×, 69×, and 8× improvement on delay fault diagnosis resolution. Furthermore, the proposed technique can be easily integrated with commercial tools.

In lower technology nodes, cases are rising where silicon behavior is unexpected under the applications of a traditional fault model-based test vector. For example, a Transition Delay Fault (TDF) based test vector expected to catch timing sensitive defects which should have frequency dependency. The expected behavior would be a reducing error counts (even a small passing region) with higher voltage and lower frequency. But often hard/static failures (no passing region across voltage/Frequency) are being observed with TDF pattern set. A hard failure may indicate a cell internal open defect which is accidently triggered by TDF two cycle patterns. To understand these silicon failures, it is important to generate test vectors targeting special input combinations for all the standard cells in the design. EDA industry provides the solution using the proposed ‘Cell Aware’ fault model. However, in this paper, we talk about different types of in-house custom fault modelling which can be generated in ‘logical space’. The paper talk in details of the methodology of these in-house fault models, compares them, and finally use failure analysis (FA) to prove the effectiveness of the fault model.

Scan chain diagnosis plays a key role in ramping up production yield. However, this is challenged by high test compression ratios of modern designs, increasing the probability of multiple faulty chains feeding the same compressor. In our analyzed silicon data, we observe that 8.76% of scan chain failures have such two faulty chains. We propose a technique to help address this problem, separating the superposition of chain fault effects to diagnose these chips. This technique first uses jump simulation to identify and classify failures that are attributable to only one of the faulty chains. It then uses commercial tools to diagnose the classified failures of each chain individually. Experiments are conducted on both simulated and silicon test data to show the efficacy of our technique, and the proposed method showed improvements over standard diagnosis with commercial tools in resolution (2.38 candidates) and accuracy (92.0%). This method was also applied on industrial chips with potentially systematic double faulty chain failures.

Debug of failing tests during new product introduction is a human-time-intensive task, requiring the focus of domain experts to develop and execute fact-finding experiments. With the increasing size and complexity of modern integrated circuit products, and the increasing size of company product portfolios, it is challenging and taxing for these few experts to support all required debug. To overcome this bottleneck of limited expertise, we propose AAA, a rule-based expert system to perform automated, on-the-tester debug of failing tests. The system is designed to replicate the typical procedure followed by an expert, including the dynamic creation and application of targeted debug tests, collection of on-tester silicon failure results, and analysis of the results to improve root-cause understanding. AAA performance is demonstrated on industrial chips with scan chain failures.

Volume diagnosis and debug play a key role in identifying systematic test failures caused by manufacturing defectivity, design marginalities, and test overkill. However, diagnosis tools often suffer from poor diagnosis resolution. In this paper, we propose techniques to improve diagnosis resolution by test failure clustering and reorganization. The effectiveness of our techniques is demonstrated on two industrial designs in cutting-edge process nodes and verified by targeted analysis and testing. The number of suspects is reduced by 3.1x and 575.2x on average. The proposed techniques can be implemented using existing commercial diagnosis tools with runtime overheads below 1%.

Hold-time faults can occur in complex designs but can be difficult to diagnose. This paper presents a systematic hold-time diagnosis method for logic circuits. A four-phase flow is introduced to solve the problem. The identification phase identifies groups of systematic error logs by systematic errors. The filtering phase builds a majority error log to avoid the effect of random defects. The verification phase verifies that the candidate fault is a hold-time fault and recognizes capture flip-flops. The determination phase determines the fault models and their corresponding faulty flip-flops. Experiments on two industrial cases show the effectiveness of our technique, both of which have been verified through root-cause analysis. The proposed technique outperforms standard diagnosis performed by a commercial tool.

Multi-capture-clock scan patterns for the traditional stuck-at-fault model have been used to reduce down pattern counts while still maintaining high test coverage. This paper studies how the same test patterns provide a decent N-detect fault coverage.