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Felix Sutton

dblp:09/10875 · DBLP profile ↗
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23ranked-venue papers
11as first author
6since 2021 · last 2025
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 13 · 10 first-author · 1 since 2021Systems, architecture and hardware · 2 · 2 since 2021Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
9 papers
Embedded and real-time systems · 52% Interconnection networks and networks-on-chip · 17% Energy-efficient computing · 12%
Computer networks
10 papers
Internet of things and sensor networks · 100%
Interdisciplinary, comprehensive, and emerging computing
2 papers
Energy systems and smart grids · 75% Environmental and earth informatics · 25%

Topics — the 23 heaviest of 26, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Internet of things and sensor networks
wireless sensor network
2.0102022
The Design of a Battery-Less Wireless Condition Monitoring System for Industrial Circuit Breakers · SenSys 2022
Mitigating Erroneous Wake-ups · SenSys 2017
Poster Abstract: A Heterogeneous System Architecture for Event-Triggered Wireless Sensing · IPSN 2016
Embedded and real-time systems › embedded hardware platform
wireless embedded platform
0.732015
Demo: Building Reliable Wireless Embedded Platforms using the Bolt Processor Interconnect · SenSys 2015
Bolt: A Stateful Processor Interconnect · SenSys 2015
Predictable wireless embedded platforms · IPSN 2015
Embedded and real-time systems › intermittent computing
batteryless sensing
0.612022
The Design of a Battery-Less Wireless Condition Monitoring System for Industrial Circuit Breakers · SenSys 2022
Internet of things and sensor networks › wireless sensor network › wireless sensor network routing
flooding
0.422015
Zippy: On-Demand Network Flooding · SenSys 2015
Wake-up flooding: an asynchronous network flooding primitive · IPSN 2015
Interconnection networks and networks-on-chip
multiprocessor interconnection
0.422015
Demo: Building Reliable Wireless Embedded Platforms using the Bolt Processor Interconnect · SenSys 2015
Bolt: A Stateful Processor Interconnect · SenSys 2015
Embedded and real-time systems › embedded hardware platform
dual processor platform
0.412019
The dual processor platform architecture: demo abstract · IPSN 2019
Internet of things and sensor networks › low-power wireless
wake-up receiver
0.312017
Mitigating Erroneous Wake-ups · SenSys 2017
Internet of things and sensor networks › wireless sensor network
event-triggered sensing
0.212016
Poster Abstract: A Heterogeneous System Architecture for Event-Triggered Wireless Sensing · IPSN 2016
GPUs and heterogeneous computing › heterogeneous architecture
heterogeneous system architecture
0.212016
Poster Abstract: A Heterogeneous System Architecture for Event-Triggered Wireless Sensing · IPSN 2016
Internet of things and sensor networks › wireless sensor network
wake-up radio
0.212015
Wake-up flooding: an asynchronous network flooding primitive · IPSN 2015
Distributed systems › operating system support › interprocess communication
asynchronous message passing
0.212015
Predictable wireless embedded platforms · IPSN 2015
Interconnection networks and networks-on-chip
interprocessor communication
0.212015
Bolt: A Stateful Processor Interconnect · SenSys 2015
Processor architecture and microarchitecture
multiprocessor architecture
0.212015
Bolt: A Stateful Processor Interconnect · SenSys 2015
Energy-efficient computing › power management
dynamic power management
0.212014
Dynamic power management for long-term energy neutral operation of solar energy harvesting systems · SenSys 2014
Embedded and real-time systems
energy harvesting systems
0.212014
Dynamic power management for long-term energy neutral operation of solar energy harvesting systems · SenSys 2014
Energy-efficient computing › energy harvesting
energy-neutral operation
0.212014
Dynamic power management for long-term energy neutral operation of solar energy harvesting systems · SenSys 2014
Embedded and real-time systems › resource-constrained computing
resource-constrained embedded system
0.212014
Demonstration abstract: automatic speech recognition for resource-constrained embedded systems · IPSN 2014
Internet of things and sensor networks
networked embedded systems
0.112019
The dual processor platform architecture: demo abstract · IPSN 2019
Energy-efficient computing › low-power design
ultra-low power design
0.112017
Mitigating Erroneous Wake-ups · SenSys 2017
Internet of things and sensor networks › energy efficiency
energy-delay tradeoff
0.112015
Wake-up flooding: an asynchronous network flooding primitive · IPSN 2015
Internet of things and sensor networks
energy efficiency
0.112015
Zippy: On-Demand Network Flooding · SenSys 2015
Natural language and speech › Speech recognition and synthesis › automatic speech recognition
embedded speech recognition
0.112014
Demonstration abstract: automatic speech recognition for resource-constrained embedded systems · IPSN 2014
Environmental and earth informatics
environmental monitoring
0.112014
Dynamic power management for long-term energy neutral operation of solar energy harvesting systems · SenSys 2014

Methods — techniques the papers use, named apart from their topics

temperature monitoring · 1.7energy harvesting · 1.7asynchronous message passing · 1.2hardware partitioning · 0.8time-domain feature extraction · 0.6classifier · 0.6heterogeneous platform design · 0.5platform partitioning · 0.4interconnect design · 0.4formal timing analysis · 0.2asynchronous rendezvous · 0.2trace-driven simulation · 0.2WCMA · 0.2EWMA · 0.2ENO-MAX · 0.2wireless embedded devices · 0.2multi-hop protocols · 0.2
YearPublicationVenuePosition
2025 A Framework for Energy Efficiency Analysis and Optimal Sizing of Industrial Motors
abstract
Electric motors account for a substantial portion of electricity usage in industrial sectors. Significant energy savings can be achieved by using high-efficiency motors and Variable Speed Drives (VSDs). However, to maximize energy efficiency, it is crucial to ensure motors are properly sized, as even VSDs cannot compensate for the inefficiencies of incorrectly sized motors. This paper tackles the issue of motor sizing, which requires a detailed evaluation of operational losses and the selection of appropriate motor specifications. To address this, we introduce a framework that integrates various motor loss prediction models, facilitates comprehensive energy efficiency assessment, and offers recommendations for motor specifications that meet the operational requirements. The framework aims to improve energy efficiency, lower operational costs, and promote sustainable operations in industrial environments.
Giacomo Garegnani, Thanikesavan Sivanthi, Philipp Sommer, Felix Sutton
ETFA5
2024 Secure On-The-Fly Firmware Updates for Safety Critical Embedded Systems
abstract
Failures in safety-critical embedded systems can result in loss of life, environmental damage or significant property damage. Examples include control systems for commercial industries, but also protection devices in residential settings. The reliability of such systems depends on their ability to periodically execute safety-related software tasks without interruption. When updating the firmware of such safety-critical embedded systems, execution is suspended until the update is complete. This suspension, or down-time, needs to be minimized or avoided completely in order to mitigate the resulting safety risks. Here, we present the design and implementation of a secure on-the-fly method for firmware updates that minimizes the down-time of safety-critical embedded systems during firmware updates. Design considerations based on the hardware capabilities of typical micro-controllers are highlighted, a software architecture is detailed, and an experimental evaluation of the down-time and memory requirements demonstrate that the proposed approach facilitates secure on-the-fly firmware updates for general safety-critical embedded applications.
Philipp M. Scholl, Felix Sutton, Philipp Sommer
ETFA2
2022 SMiLe: Automated End-to-end Sensing and Machine Learning Co-Design
Tanmay Goyal, Pengcheng Huang 0001, Felix Sutton, Balz Maag, Philipp Sommer
EWSN3
2022 Poster: Empirical Evaluation of AutoML Algorithms for Motor Health Prediction
Tanmay Goyal, Pengcheng Huang 0001, Felix Sutton, Balz Maag, Philipp Sommer
EWSN3
2022 The Design of a Battery-Less Wireless Condition Monitoring System for Industrial Circuit Breakers
abstract
Circuit breakers are a fundamental safety device in all residential and industrial electrical distribution installations. The harsh environmental conditions of industrial circuit breakers can lead to unwanted resistance, i.e., due to the build-up of dirt, between the circuit breaker terminals and the conducting metal bars that supply power from the grid. This can lead to excessive heat through the circuit breaker mechanics, which over time, may degrade the lifetime of the circuit breaker. In order to mitigate this, a monitoring system is needed to remotely monitor the temperature of the circuit breaker contact terminals, thus improving scheduled maintenance and minimizing downtime.
Felix Sutton
SenSys1
2021 VIADUCT: Bridging the Gap between Testbeds and Real-World Cyber-Physical Systems
Philipp Sommer, Felix Sutton
EWSN2
2019 The dual processor platform architecture: demo abstract
abstract
The Dual Processor Platform (DPP) is a novel architecture template for networked embedded systems based on a strictly asynchronous processor interconnect that allows to minimize interference with a proven predictable behavior [7]. Contrary to traditional platforms [1, 5] DPP tries to mitigate interference by isolating different tasks and mapping them onto dedicated hardware resources. Typically, two different task sets - (i) sensing/actuation/data processing and (ii) communication - are mapped onto two different physically separated processing elements (usually low-power microcontrollers), allowing each to be optimized according to their individual requirements. Such hardware partitioning is a standard approach, frequently found in more complex sensor system implementations [2]. While the communication processor handles wireless packet transmission and reception, the application processor is dedicated to the sensor data acquisition, processing and actuation. But this strict separation of resources and function also requires a processor interconnect: BOLT [7], a stateful processor interconnect specifically designed based on this paradigm allows a strict decoupling of the power, clock and time domains of the two processing elements by allowing only asynchronous message passing between the two. The strict limitation to an asynchronous interface allows for predictable run-time behavior that, in addition to typical behavior observed from experiments, has been formally verified [7]. The most notable advantages of this approach are:
Jan Beutel, Roman Trüb, Reto Da Forno, Markus Wegmann, Tonio Gsell, Romain Jacob, Michael Keller, Felix Sutton, Lothar Thiele
IPSN8
2019 BLITZ: Low Latency and Energy-Efficient Communication for Event-Triggered Wireless Sensing Systems
abstract
Event-triggered wireless sensing systems are an important class of wireless sensor network, where the detection of non-deterministic events enables the monitoring and control of processes in industries such as manufacturing, healthcare, and agriculture. The system properties of low latency, energy efficiency, and adaptability make event-triggered wireless sensing systems a key technological enabler for the Industrial Internet of Things. <?tight?>Wireless sensing systems based on periodic multi-hop communication exhibit a fundamental trade-off between latency and energy efficiency, which is unfavorable for event-triggered application scenarios. To address this technological gap, we present B litz , the first communication architecture that combines asynchronous and synchronous flooding primitives to facilitate low latency and energy-efficient multi-hop communication of non-deterministic events. B litz also incorporates a novel scheme for mitigating erroneous wake-ups, which is shown analytically and experimentally to further reduce energy consumption. We present a prototype implementation of B litz and evaluate its performance in an indoor testbed deployment. Experiments show that BLITZ supports a mean latency as low as 108.9ms for an 8-bit event packet and its associated data packet of 32 bytes through a 4-hop network, and a power dissipation of 16μW during periods of inactivity.
Felix Sutton, Reto Da Forno, Jan Beutel, Lothar Thiele
ACM Trans. Sens. Networks1
2017 Competition: Robust Flooding using Back-to-Back Synchronous Transmissions with Channel-Hopping
Roman Lim, Reto Da Forno, Felix Sutton, Lothar Thiele
EWSN3
2017 The Design of a Responsive and Energy-efficient Event-triggered Wireless Sensing System
Felix Sutton, Reto Da Forno, David Gschwend, Tonio Gsell, Roman Lim, Jan Beutel, Lothar Thiele
EWSN1
2017 Mitigating Erroneous Wake-ups
abstract
We propose a novel method for mitigating erroneous wake-ups that are commonly associated with ultra-low power wake-up receivers. Recent research in low-power protocols has demonstrated significant improvements in energy-efficiency by employing ultra-low power wake-up receivers. However, due to the low-complexity receiver structures adopted, wake-up receivers are susceptible to external interference, which can cause the detection of non-existent wake-ups. The occurrence of these erroneous wake-ups wastes precious energy resources, thereby negating the potential energy savings in employing wake-up receivers. We address this challenging problem by extracting time-domain features from the output of the wake-up receiver, and construct a classifier to distinguish between correct and erroneous wake-ups. We describe the design of the proposed wake-up classifier and present preliminary results.
Felix Sutton, Jan Beutel, Lothar Thiele
SenSys1
2016 Poster Abstract: A Heterogeneous System Architecture for Event-Triggered Wireless Sensing
abstract
We present a heterogeneous system architecture for event-triggered wireless sensing capable of supporting high spatial resolution. The key differentiator between the proposed architecture and alternative state-of-the-art approaches is the ability to simultaneously maximize operational lifetime and minimize end-to-end latency of detected events. Our novel architecture takes advantage of heterogeneity with respect to the operation of the wireless communication protocol and the construction of the sensing platform. We present a two-hop proof of concept implementation, exhibiting end-to-end latencies on the order of tenths of a second, while dissipating on the order of tens of microwatts during periods of inactivity.
Felix Sutton, Reto Da Forno, David Gschwend, Roman Lim, Tonio Gsell, Jan Beutel, Lothar Thiele
IPSN1
2016 On platforms for CPS - adaptive, predictable and efficient
abstract
If visions and forecasts of industry come true then we will be soon surrounded by billions of interconnected embedded devices. We will interact with them in a cyber-human symbiosis, they will not only observe us but also our environment, and they will be part of many visible and ubiquitous objects around us. The information that is collectively gathered and analyzed is supposed to help us in our daily live, in making faithful decisions, but it will also directly be used for actuation and it will cause changes by means of local and global control loops.
Lothar Thiele, Felix Sutton, Romain Jacob, Roman Lim, Reto Da Forno, Jan Beutel
RSP2
2015 Predictable wireless embedded platforms
abstract
Resource interference is a fundamental barrier to realizing predictable wireless embedded systems. We address this problem by (i) partitioning application and communication tasks onto dedicated platforms, and (ii) designing a platform interconnect to facilitate asynchronous message exchange with predictable run-time behavior. We motivate the need for this platform interconnect, termed Bolt, and describe a prototype implementation. Evaluation results indicate that the developed platform interconnect exhibits tightly bounded run-time execution with low jitter, and a negligible resource overhead with respect to state-of-the-art application and communication platforms.
Felix Sutton, Reto Da Forno, Marco Zimmerling, Roman Lim, Tonio Gsell, Federico Ferrari, Jan Beutel, Lothar Thiele
IPSN1
2015 Wake-up flooding: an asynchronous network flooding primitive
abstract
We present a new technique for overcoming the fundamental trade-off between energy-efficiency and end-to-end packet latency pervading all event-triggered wireless sensing applications. Instead of applying popular synchronous or pseudo-asynchronous protocols, we leverage state-of-the-art wake-up receivers to facilitate purely asynchronous rendezvous. We then extend the per-hop asynchrony into a multi-hop flooding primitive, termed Wake-up Flooding. We describe the underpinnings of the flooding primitive and present preliminary results of wake-up flooding implemented on a custom dual-radio wireless sensing platform deployed in an indoor testbed.
Felix Sutton, Lothar Thiele
IPSN1
2015 Zippy: On-Demand Network Flooding
abstract
In this paper, we tackle the challenge of rapidly disseminating rare events through a multi-hop network, while achieving unprecedented energy-efficiency. Contrary to state-of-the-art approaches, we circumvent the undesirable trade-offs associated with low-power duty-cycled protocols and backscatter technologies, and demonstrate a paradigm shift in low-power protocol design. We present Zippy, an on-demand flooding technique that provides robust asynchronous network wake-up, fine-grained per-hop synchronization and efficient data dissemination by leveraging low-complexity transmitter and receiver hardware. We are the first to demonstrate the on-demand flooding of rare events through a multi-hop network with end-to-end latencies of tens of milliseconds, while dissipating less than 10 microwatts during periods of inactivity. We present a prototype implementation of our proposed approach using a wireless sensor platform constructed from commercially available components. We extensively evaluate Zippy's performance in a laboratory setting and in an indoor testbed.
Felix Sutton, Bernhard Buchli, Jan Beutel, Lothar Thiele
SenSys1
2015 Bolt: A Stateful Processor Interconnect
abstract
The wireless sensor network community is currently undergoing a platform paradigm shift, moving away from classical single-processor motes toward heterogeneous multi-processor architectures. These emerging platforms promise efficient concurrent processing with energy-proportional system performance. The use of shared interconnects and shared memory for inter-processor communication, however, causes interference in the time, power, and clock domains, which prevents designers from fully harnessing these benefits. We thus designed Bolt, the first ultra-low-power processor interconnect for the compositional construction of heterogeneous wireless embedded platforms. This paper presents the architectural blueprint for interconnecting two independent processors, while enabling asynchronous inter-processor communication with predictable run-time behavior. We detail a prototype implementation of Bolt, and apply formal methods to analytically derive bounds on the execution time of its message passing operations. Experiments with a custom-built dual-processor platform show that our Bolt prototype incurs a negligible power overhead relative to state-of-the-art platforms, offers predictable message passing with empirical bounds that match the analytical ones to within a few clock cycles, and achieves a high throughput of up to 3.3 Mbps.
Felix Sutton, Marco Zimmerling, Reto Da Forno, Roman Lim, Tonio Gsell, Georgia Giannopoulou, Federico Ferrari, Jan Beutel, Lothar Thiele
SenSys1
2015 Demo: Building Reliable Wireless Embedded Platforms using the Bolt Processor Interconnect
abstract
We demonstrate the capabilities of Bolt, an ultra-low-power processor interconnect for the composable construction of new multi-processor wireless embedded platforms. Bolt provides asynchronous bidirectional communication between two processors with predictable message transfer times. In this way, Bolt solves the resource interference problem inherent in today's wireless embedded platforms, enabling simpler and more robust system designs with minimal resource overhead. Using our Bolt prototype implemented on a state-of-the-art microcontroller, we demonstrate Bolt's composability and decoupling in time, power, and clock domains.
Felix Sutton, Marco Zimmerling, Reto Da Forno, Roman Lim, Tonio Gsell, Georgia Giannopoulou, Federico Ferrari, Jan Beutel, Lothar Thiele
SenSys1
2014 Towards Enabling Uninterrupted Long-Term Operation of Solar Energy Harvesting Embedded Systems
Bernhard Buchli, Felix Sutton, Jan Beutel, Lothar Thiele
EWSN2
2014 Demonstration abstract: automatic speech recognition for resource-constrained embedded systems
Felix Sutton, Reto Da Forno, Roman Lim, Marco Zimmerling, Lothar Thiele
IPSN1
2014 Dynamic power management for long-term energy neutral operation of solar energy harvesting systems
abstract
In this work we consider a real-world environmental monitoring scenario that requires uninterrupted system operation over time periods on the order of multiple years. To achieve this goal, we propose a novel approach to dynamically adjust the system's performance level such that energy neutral operation, and thus long-term uninterrupted operation can be achieved. We first consider the annual dynamics of the energy source to design an appropriate power subsystem (i.e., solar panel size and energy store capacity), and then dynamically compute the long-term sustainable performance level at runtime. We show through trace-driven simulations using eleven years of real-world data that our approach outperforms existing predictive, e.g., EWMA, WCMA, and reactive, e.g., ENO-MAX, approaches in terms of average performance level by up to 177%, while reducing duty-cycle variance by up to three orders of magnitude. We further demonstrate the benefits of the dynamic power management scheme using a wireless sensor system deployed for environmental monitoring in a remote, high-alpine environment as a case study. A performance evaluation over two years reveals that the dynamic power management scheme achieves a two-fold improvement in system utility when compared to only applying appropriate capacity planning.
Bernhard Buchli, Felix Sutton, Jan Beutel, Lothar Thiele
SenSys2
2013 A reliable wireless nurse call system: overview and pilot results from a summer camp for teenagers with duchenne muscular dystrophy
abstract
We present the design of a reliable nurse call system based on wireless embedded devices and multi-hop protocols. Our work is motivated by the need for such system during annual summer camps for people with muscular dystrophy and the lack of suitable alternative solutions. We describe how our prototype meets the reliability and real-time requirements of such system, and report on results from a two-week deployment during a camp with 13 affected boys in July 2013.
Marco Zimmerling, Federico Ferrari, Roman Lim, Olga Saukh, Felix Sutton, Reto Da Forno, Remo S. Schmidt, Marc André Wyss
SenSys5
2012 GPS-Equipped Wireless Sensor Network Node for High-Accuracy Positioning Applications
Bernhard Buchli, Felix Sutton, Jan Beutel
EWSN2