As multi-core processor technology advances and integration levels increase, effective chip temperature management significantly impacts performance and energy efficiency. However, in high power environments, relying on traditional dynamic thermal management methods (such as adjusting voltage and frequency) is no longer sufficient to effectively control and regulate the temperature of processors. This paper introduces a reinforcement learning modeling approach based on a core thermal model, which combines a more accurate processor state model with reinforcement learning techniques. It also utilizes an adaptive dueling DQN architecture, which helps agents learn more effective thermal-aware task scheduling during the training process. Compared to other methods, this approach reduces the average and peak temperatures by at least 2.06°C and 2.47°C respectively. Additionally, under stricter time constraints, processor performance is maintained while reducing core temperature.

The dark silicon issue is a significant challenge faced by chip manufacturers today, requiring them to find ways to enhance the performance of systems with limited power consumption. This necessitates the implementation of a power distribution method to control the system’s power usage while operating within thermal safety limits. However, due to the complex nature of heterogeneous systems, there are currently limited solutions available for effectively managing the power budgeting problem in such systems. This paper presents a simple and effective power budgeting method called Boundary Search-based Power Budgeting for heterogeneous systems (BSP). Under steady-state conditions, BSP divides the original cores into thermal spots of equal size based on the side lengths of the cores. By transforming the heterogeneous system into a homogeneous system in this way, we then apply our composite power budgeting method to the partitioned system, thus achieving power budgeting for the heterogeneous system. Experiments show that BSP has simplified the heterogeneous system and maximized the power budget while ensuring system performance.

Compositional Zero-Shot Learning (CZSL) aims to learn visual concepts (i.e., attributes and objects) from seen compositions and combine them to predict unseen compositions. Existing visual encoders in CZSL typically use traditional visual encoders (i.e., CNN and Transformer) or image encoders from Visual-Language Models (VLMs) to encode image features. However, traditional visual encoders need more multi-modal textual information, and image encoders of VLMs exhibit dependence on pre-training data, making them less effective when used independently for predicting unseen compositions. To overcome this limitation, we propose a novel approach based on the joint modeling of traditional visual encoders and VLMs visual encoders to enhance the prediction ability for uncommon and unseen compositions. Specifically, we design an adaptive fusion module that automatically adjusts the weighted parameters of similarity scores between traditional and VLMs methods during training, and these weighted parameters are inherited during the inference process. Given the significance of disentangling attributes and objects, we design a Multi-Attribute Object Module that, during the training phase, incorporates multiple pairs of attributes and objects as prior knowledge, leveraging this rich prior knowledge to facilitate the disentanglement of attributes and objects. Building upon this, we select the text encoder from VLMs to construct the Adaptive Fusion Network. We conduct extensive experiments on the Clothing16 K, UT-Zappos50 K, and C-GQA datasets, achieving excellent performance on the Clothing16 K and UT-Zappos50 K datasets.

Dark silicon is a phenomenon of under-utilization in today's manycore systems due to power and thermal limitations. In order to improve the performance of dark silicon systems, it is necessary to adopt dynamic power constraints for different core mapping decisions. However, existing power budgeting methods are generally over pessimistic, e.g., Thermal Safe Power (TSP), or over optimistic, e.g., Greedy based Dynamic Power (GDP). This paper proposes a practical power budgeting method, called Combinational Optimization Power (COP). Different from existing methods, which ignore some actual factors, such as communication overhead and lifetime reliability, COP formulates the power budgeting problem as a thermal-constrained combinational optimization power problem. For the steady-state case, COP achieves the target fusion of optimized temperature and communication energy consumption by applying task priority ranking and task-to-core mapping. For the transient case, COP uses the rainflow counting algorithm to construct the reliability framework based on the thermal cycling failure mechanism, and then establishes a linear time-invariant transient temperature model to obtain the core mapping selection and the corresponding dynamic power budget. Experimental results demonstrate that COP is capable of providing an optimized core mapping decision, which can maximize power budget while ensuring the system performance.

In order to improve the performance of many-core systems, it is necessary to adopt dynamic power constraints for different core mapping decisions. However, existing power budgeting methods are generally over pessimistic, e.g. Thermal Safe Power (TSP), or over optimistic, e.g. Greedy based Dynamic Power (GDP). This paper proposes a practical power budgeting method, called Combinational Optimization Power (COP). Different from existing methods, which ignore some actual factors, such as communication overhead and lifetime reliability, COP formulates the power budgeting problem as a thermal-constrained combinational optimization power problem. For the steady-state case, COP achieves the target fusion of optimized temperature and communication energy consumption by applying task priority ranking and task-to-core mapping. For the transient case, COP uses the rainflow counting algorithm to construct the reliability framework based on the thermal cycling failure mechanism, and then establishes a linear time-invariant transient thermal model to obtain the core mapping selection and the corresponding dynamic power budget. Experimental results show that COP is capable of providing an optimized core mapping decision, which can maximize power budget while ensuring the system performance.

Thermal issues seriously restrict the quality, reliability, and lifetime of semiconductor chips. To prevent thermal runaway situations, modern processors deploy numerous on-die thermal sensors to collect temperature information, which is then used to guide dynamic thermal management (DTM) mechanisms. Accurate on-chip temperature information is critical for DTM as temperature overestimation will degrade the performance by an unnecessary invocation of thermal control mechanisms, and underestimation will result in the reliability issues of the systems. In this article, two effective techniques are proposed to achieve an accurate on-chip temperature sensing. The first technique is a synergistic calibration method for forecasting the actual temperatures of noisy thermal sensors. Second, we propose a full thermal characterization technique based on convolutional neural networks (CNNs) to accurately recover the entire thermal maps by using a limited number of thermal sensors. In a realistic scenario, these two techniques can be used in combination to provide a more accurate thermal monitoring. By utilizing the sophisticated infrared imaging setup, the effectiveness of the proposed techniques is validated on a real 45-nm AMD quad-core chip. The simulation results show that the methods achieve significant improvements compared with existing techniques in the literature. The successful implementation of the proposed methods will significantly improve the efficiency of DTM.

Thermal issues are a major concern in high-end computing systems as they severely constrain the performance and shorten the lifetime of integrated circuits. Using embedded on-die thermal sensors, state-of-the-art processors widely employ dynamic thermal management (DTM) mechanisms to prevent thermal runaway situations in multi-core architectures. Full thermal characterization is particularly useful for fine-grained thermal management techniques, examples of which include per-core workload scheduling, and voltage and frequency scaling. In this paper, a new direction for full thermal reconstruction of multi-core processors is proposed based on convolutional neural networks (CNNs) to precisely recover the overall thermal maps from a small number of sensors. The effectiveness of our method is verified on a real AMD quad-core processor. Experimental results indicate that the proposed method is capable of handling high-resolution thermal extraction, and achieves significant improvements compared to available techniques in the literature. The main contribution of this work is to demonstrate the ability of deep learning approaches for full thermal reconstruction of semiconductor chips. The success of our proposed method will assist DTM to achieve a more accurate thermal monitoring.

Embedded thermal sensors are very susceptible to a variety of noise sources, including environmental uncertainty and process variation. This causes the discrepancies between actual temperatures and those observed by on-chip thermal sensors, which seriously affect the efficiency of dynamic thermal management (DTM). In this paper, a smoothing filter-based Kalman prediction technique is proposed to estimate the accurate temperatures of noisy sensors. On this basis, a multi-sensor synergistic calibration algorithm is proposed to improve the simultaneous prediction accuracy of multiple sensors. Moreover, an infrared imaging-based temperature measurement technique is also proposed to capture the thermal traces of an AMD quad-core processor in real-time. The acquired real temperature data are used to evaluate our prediction performance. Simulation shows that the synergistic calibration scheme can achieve an average reduction of the root-mean-square error (RMSE) by 75.9% compared with assuming the thermal sensor readings to be ideal. Additionally, the average false alarm rate (FAR) of the corrected sensor temperature readings can be reduced by 21.6%. These results clearly demonstrate that if our approach is used to perform the temperature estimation, the response mechanisms of DTM can be triggered to adjust the voltages, frequencies, and cooling fan speeds at more appropriate times.

High-performance processors utilize embedded thermal sensors to continuously monitor the temperature of the chip during runtime. However, the overheating locations change temporally and spatially, depending on the various workloads running on the chip. Moreover, on-chip thermal sensor readings are highly affected by noise due to fabrication variations and randomness, which make the task of thermal monitoring particularly challenging. In this paper, we establish overheating detection models to address the thermal sensor allocation problem under two different conditions, when the on-chip thermal sensor observations are corrupted by noise. On this basis, a heuristic method based on genetic algorithm (GA) is proposed to find a near-optimal thermal sensor allocation solution that can significantly improve overheating detection probability, while greatly reducing execution time. We also propose a hybrid algorithm to identify the optimal thermal sensor placement for each individual chip block or component. Furthermore, we develop an oil-based cooling system, and utilize infrared thermal imaging techniques to capture the thermal traces of a real dual-core microprocessor running on various workloads. Experimental results demonstrate that our proposed thermal sensor allocation algorithms clearly outperform several common allocation approaches in terms of overheating detection, which can provide accurate and reliable thermal monitoring.