Phase transition materials (PTMs) have drawn significant attention in recent years due to their abrupt threshold switching characteristics and hysteretic behavior. Augmentation of the PTM with a transistor has been shown to provide enhanced selectivity (as high as ~107 for Ag/HfO2/Pt) leading to unique circuit-level advantages. Previously, a unipolar PTM, Ag-HfO2-Pt, was reported as a replacement for diodes due to its polarity-dependent high selectivity and hysteretic properties. It was shown to achieve ~50% higher-DC output compared to a diode-based design in a Cockcroft-Walton multiplier circuit. In this article, we take a deeper dive into this design. We augment two different PTMs (unipolar Ag-HfO2-Pt and bipolar VO2) with diode-connected MOSFETs to retain the benefits of hysteretic rectification. Our proposed hysteretic diodes (Hyperdiodes) exhibit a low-forward voltage drop owing to their volatile hysteretic characteristics. However, augmenting a hysteretic PTM with a transistor brings an additional stability concern due to their complex interplay. Hence, we perform a comprehensive stability analysis for a range of threshold voltages (−0.2 V$V_{\mathrm { th}}$$3 {\sigma }$Monte-Carlo variation analysis for a Cockcroft-Walton multiplier considering the nonidealities in the host transistor and the PTM. We observe that, hyperdiode-based design achieves ~20% higher-output voltage compared with the conventional designs within a fixed timeframe ($200~\boldsymbol {\mu }$s).

Modern applications such as the Internet of Things (IoT) devices, AI, and automotive applications widely use field-programmable gate arrays (FPGAs). However, many of these applications have limited power resources. Also, the existing FPGAs are vulnerable to side-channel attacks (SCAs) such as correlation-based power analysis (CPA) attacks. Therefore, designing low-power, CPA-resistant, and secure-by-design FPGA is required. In this article, two low-power and CPA-resistant hybrid CMOS/magnetic tunnel junction (MTJ) logic-in-memory-based configurable logic blocks (CLBs) have been proposed and compared to a state-of-the-art counterpart. The first proposed design is single output, and the second one is multioutput. The simulation results show that compared to the state-of-the-art secure CLB counterpart [secured CLB (sCLB) by Zooker et al. (2020)], the proposed CLB designs have 42% and 33% lower delay, 85% and 18% lower power consumption, and 86% and 63% fewer equivalent transistors. To implement one round of the PRESENT algorithm, the first and second designs have 85% and 77% fewer transistors, 42% and 33% lower delay, and 86% and 50% lower power consumption compared to their silicon-proven secure counterpart. Also, to implement convolution layers of binarized neural network (BNN), compared to this counterpart, the first and second proposed designs have 85% and 90% fewer equivalent transistors, 42% and 33% lower delay, and 86% and 79% lower power consumption. Also, the resiliency of the proposed designs against power analysis attacks has been investigated by exhaustive simulations and performing CPA attacks on PRESENT and Advanced Encryption Standard (AES) SBOX. Also, this resiliency has been investigated for different tunnel magnetoresistance ratios (TMRs) and supply voltages.

Neuromorphic Computing presents a resource-efficient computing paradigm by enabling brain-inspired low-power computations. This compute efficiency can be attributed in large part to the nature of analog computations and bio-inspired spiking data. However, the hardware implementation of a general-purpose or reconfigurable SRNN for neuromorphic computations poses challenges, especially pertaining to the programmable connectivity between neurons. This challenge becomes more pronounced when dealing with analog spikes, where information is encoded in the timing, width, shape, and frequency components of the spikes. Existing approaches to reconfigurable spike routing Network-on-Chip (NoC) architectures are predominantly packet-based, falling short when preserving the majority of information within the spike. This becomes especially problematic for small-scale SRNNs, where these packet-based approaches lead to information loss while introducing unnecessary overhead, leading to increased power consumption and NoC implementation area on-chip. To address this challenge, this work introduces AnSpiCS-Net: Analog Spike routing Circuit Switched Network-on-Chip. AnSpiCS-Net utilizes a circuit-switching-based architecture with a Clos network topology, employing three distinct switch types: transmission gates, NMOS, and PMOS switches. The NMOS switch-based configuration achieves a balanced performance across various design metrics, while the transmission gate configuration excels in spike signal integrity. Various implementations of AnSpiCS-Net are assessed based on critical implementation metrics, including latency, throughput, power consumption, and area. AnSpiCS-Net proves highly efficient, offering nearly a 48x reduction in area for the transmission gate-based configuration compared to packetized NoC architectures in existing literature.

Machine learning based on memristive dot product engine (DPE) suffers from some practical limitations of memristive synapse which requires constraining the resources such as the number of memristive states and current sensing capability at the classification layer. Constraining those resources saves design time, complexity, and resources but impacts the performance of the system. This paper assesses the performance of DPE-based machine learning across different numbers of memristive states and varying the current sensing resolution at the classification layer. The study found that, for small applications, 8 memristive states are sufficient, with minimal impact observed from increasing the number of states with lower current distinguishability. The analysis also finds that the decreasing current sensing resolution negatively impacts the stability of the system by increasing the random behavior.

In order for raw sensory data to be processed by spiking neural networks (SNNs) an intermediary spike encoder must translate that data into a spike-train. Since there is no one-size-fits-all encoding method suitable for every neuromorphic application, the necessary encoding scheme differs from one implementation to the next. A similar circumstance exists concerning the encoding interval, or frame, that a spike-train is produced for. Although research exists on individual encoding schemes with a rationale for excluding other methods for a particular application, no neuromorphic implementation has addressed a dedicated hardware encoder that is compatible with multiple encoding methods. In this study, we introduce an encoder module which supports three major encoding schemes. The encoding method, as well as the encoding frame duration, can be easily tweaked at runtime. Both FPGA and VLSI implementations have been created for this encoder that are highly scalable and fast, with the latter running with a clock frequency of up to 530 MHz in a 65-nm process. The small area and power footprint of this design makes it attractive for any hardware-based neuroprocessor without needing any external software, or hardware, based process for data encoding.

Short-term plasticity (STP) is a synaptic modification process found in biological synapses that increases the computational power of the neuronal network. To implement plasticity rules, we use a memristor-based synapse due to its inherent plasticity. The synapse is designed to operate in the low resistance state (LRS) region using a current-controlled mechanism to account for the device non-idealities encountered at the high resistance state (HRS). In this work, we implement a mixed-signal STP circuit for this synapse design. The STP circuit uses a digital part to generate pulses to initiate the weight change, and an analog part to update the programming voltage. The STP functionality is verified using a 65nm CMOS process, and the performance metrics are reported. Results show that our circuit achieves a great performance in terms of area and power consumption.

Memristors are a suitable candidate to design synapse circuits and neuromorphic systems. Due to device and voltage variability, operating a memristive device with reliability is a big challenge. To enhance the reliability of memristive synapse, RESET failure needs to be considered. In this work, we are focused on RESET failure modeling with RESET voltage variation. Here, the RESET failure is defined as hard failure of the memristive synapse due to a high RESET voltage being applied. The proposed Verilog-A model is derived based on experimental data collected from 1T1R devices, which are fabricated on 65 nm CMOS process. To enhance the reliability of system-level simulation, this device model will provide better guidelines to the designer. In addition, power consumption for a successful RESET operation is 7.065 μW at 1.5 V, which can RESET the memristor resistance from 5 kΩ to 200 kΩ.

Neuromorphic computing systems have emerged as powerful computation tools in the field of object recognition and control systems. However, training these systems, which are usually characterized by recurrent connectivity, requires abundant computational resources: memory, computation, data, and time. Reservoir computing (RC) framework reduces this high computational training cost by focusing the training effort on only a small subset of connections thus allowing these systems to be amenable to hardware implementation. Using memristors to construct these reservoir computers reduce the area/power consumption even further. However, the inherent variability of memristors poses specific challenges. Here, we conduct an in-depth reliability analysis of challenges posed by HfO2 memristors, including cycle-to-cycle variability, read/write noise, and conductance drift in the context of RC hardware. We also explore plasticity mechanisms such as Spike-Timing Dependent Plasticity (STDP) within the scope of the spiking recurrent neural networks (SRNN) reservoir and their impact on memristor conductance drift (MCD). We present a chaotic time series prediction task applied to a Python model of the constrained hardware design achieving very low Normalized Root Mean Square Error (NRMSE) of 2 × 10-3. The analog neuron and memristive synapse circuits employed for constructing the SRNN are simulated in Cadence Spectre and the energy consumption for the Mackey-Glass (MG) time-series prediction task was found to be approximately 90 nJ.

Memristors provide a tempting solution for weighted synapse connections in neuromorphic computing due to their size and non-volatile nature. However, memristors are unreliable in the commonly used voltage-pulse-based programming approaches and require precisely shaped pulses to avoid programming failure. In this paper, we demonstrate a current-limiting-based solution that provides a more predictable analog memory behavior when reading and writing memristive synapses. With our proposed design READ current can be optimized by ~19x compared to the 1T1R design. Moreover, our proposed design saves ~9x energy compared to the 1T1R design. Our 3T1R design also shows promising write operation which is less affected by the process variation in MOSFETs and the inherent stochastic behavior of memristors. Memristors used for testing are hafnium oxide based and were fabricated in a 65 nm hybrid CMOS-memristor process. The proposed design also shows linear characteristics between the voltage applied and the resulting resistance for the writing operation. The simulation and measured data show similar patterns with respect to voltage pulse based programming and current compliance based programming. We further observed the impact of this behavior on neuromorphic-specific applications such as a spiking neural network.

Neuromorphic computing is a leading option for non von-Neumann computing architectures. With it, neural networks are developed that derive architectural inspiration from how the brain operates with neurons, synapses, and spikes. These networks are often implemented in either software or hardware based neuroprocessors designed to handle specific tasks efficiently. Even if implemented in hardware, software emulation is instrumental in determining the worthwhile features and capabilities of the architecture. In this work two novel neuroprocessors are introduced: the software-based RISP neuroprocessor, and the RAVENS hardware neuroprocessor. Several benchmark tests using control applications are performed with each neuroprocessor configured in various ways to evaluate their comparative performance and training properties.

In this paper, in an effort to emulate the properties of a biological neuron in silicon, we design a mixed-signal Integrate-And-Fire (IAF) neuron with two different approaches for the refractory period mechanism. The two approaches, one digital and one analog, have been designed to behave equivalently, except for the use of external programming signals. Neurons using both refractory blocks have been simulated using a 65nm CMOS process and their performances have been quantified in terms of area and power consumption. We find that although the analog refractory block can be made smaller than the digital counterpart by using a smaller capacitor, the area-power trade-off resulting from the use of a high programming current overshadows this advantage. The digital block is also found to perform better in terms of power consumption and programming precision.

This work addresses how to naturally adopt the l 2 -norm cosine similarity in the neuromemristive system and studies the unsupervised learning performance on handwritten digit image recognition. Proposed architecture is a two-layer fully connected neural network with a hard winner-take-all (WTA) learning module. For input layer, we propose single-spike temporal code that transforms input stimuli into the set of single spikes with different latencies and voltage levels. For a synapse model, we employ a compound memristor where stochastically switching binary-state memristors connected in parallel, which offers a reliable and scalable multi-state solution for synaptic weight storage. Hardware-friendly synaptic adaptation mechanism is proposed to realize spike-timing-dependent plasticity learning. Input spikes are sent out through those memristive synapses to each and every integrate-and-fire neuron in the fully connected output layer, where the hard WTA network motif introduces the competition based on cosine similarity for the given input stimuli. Finally, we present 92.64% accuracy performance on unsupervised digit recognition with only single-epoch MNIST dataset training via high-level simulations, including extensive analysis on the impact of system parameters.

introduction Share on Introduction to the Special Issue on Hardware-Assisted Security for Emerging Internet of Things Editors: Saraju P. Mohanty University of North Texas University of North TexasView Profile , Jim Plusquellic University of New Mexico University of New MexicoView Profile , Garrett S. Rose University of Tennessee, Knoxville University of Tennessee, KnoxvilleView Profile , Wei Zhang Hong Kong University of Science and Technology Hong Kong University of Science and TechnologyView Profile , Maria K. Michael University of Cyprus University of CyprusView Profile Authors Info & Claims ACM Journal on Emerging Technologies in Computing SystemsVolume 18Issue 1January 2022 Article No.: 1pp 1–3https://doi.org/10.1145/3475952Online:29 September 2021Publication History 0citation90DownloadsMetricsTotal Citations0Total Downloads90Last 12 Months90Last 6 weeks12 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Spiking neural networks (SNN) offer a power efficient, biologically plausible learning paradigm by encoding information into spikes. The discovery of the memristor has accelerated the progress of spiking neuromorphic systems, as the intrinsic plasticity of the device makes it an ideal candidate to mimic a biological synapse. Despite providing a nanoscale form factor, non-volatility, and low-power operation, memristors suffer from device-level non-idealities, which impact system-level performance. To address these issues, this article presents a memristive crossbar-based neuromorphic system using unsupervised learning with twin-memristor synapses, fully digital pulse width modulated spike-timing-dependent plasticity, and homeostasis neurons. The implemented single-layer SNN was applied to a pattern-recognition task of classifying handwritten-digits. The performance of the system was analyzed by varying design parameters such as number of training epochs, neurons, and capacitors. Furthermore, the impact of memristor device non-idealities, such as device-switching mismatch, aging, failure, and process variations, were investigated and the resilience of the proposed system was demonstrated.

A physically unclonable and reconfigurable computing system is introduced which provides both logic locking and authentication of devices. A chaotic oscillator is required to generate the chaotic signals and can produce different Boolean functions using different tuning parameters, including a control bit, iteration number, threshold voltage, and bifurcation parameter. The aim of this article is to build a hybrid computing system with the mixed implementation of standard logic gates and reconfigurable chaos-based logic gates. The tuning parameters of the oscillator make up the secret key for logic locking. Process variation due to fabrication can be leveraged to generate unique keys for each chip. The whole computing system exhibits physical unclonable function (PUF) characteristics and can be used to generate challenge-response pairs (CRPs) for authenticating devices. We have used ISCAS'85 combinational benchmark circuits to demonstrate the results. The Hamming distance between correct and wrong outputs is calculated to ensure that 50% of the output bits are flipped when the wrong key is applied. A Boolean SAT attack has been carried out on the system and it displays exponential complexity with an increase in the total number of chaos gates and key size of each chaos gate. The hybrid system demonstrates near-ideal PUF metrics, including uniqueness, uniformity, and bit aliasing. Common machine learning attacks have been executed on the CRPs generated from the whole system and results show that the proposed chaos-based PUF is robust against modeling attacks. The hybrid system has significantly less overhead compared to traditional systems containing both logic locking and PUF circuitry.

In this work we describe the design, implementation, and testing of the first neuromorphic robot capable of obstacle avoidance, grid coverage, and targeting controlled by the second generation Dynamic Adaptive Neural Network Array (DANNA2) digital spiking neuromorphic processor. The simplicity of the DANNA2 processor along with the TENNLab hardware/software co-design framework allows for compact spiking networks that can run efficiently on a small, resource-constrained, platform such as a Xilinx Artix-7 field-programmable gate array. Additionally, we present the dynamic reconfigurability of DANNA2 arrays as a method of realizing complex, multi-objective tasks on hardware that is restricted to relatively small networks.

Designing spiking neural networks for neuromorphic deployment is a non-trivial task. It is further complicated when there are resource constraints for the neuromorphic implementation, such as size or power constraints, that may be present in edge applications. In this work, we utilize a previously presented approach, EONS, to design spiking neural networks for a memristive neuromorphic implementation for scientific data applications. We specifically use a multi-objective approach in EONS to maximize network accuracy on the scientific data application task, but also to minimize network size and energy. We illustrate that EONS determines both the network structure and the parameters, removing the burden from the user on determining the appropriate spiking neural network structure, and we show that the resulting networks are very different from the layered structure of typical neural networks. Finally, we show that the multi-objective approach produces smaller, more energy efficient networks than the original EONS approach and produces comparable accuracy to a back-propagation style training approach.

Neuromorphic computing is one promising post-Moore's law era technology, which takes inspiration from biological brains to perform computing tasks. The human brain contains billions of neurons with trillions of synapses and as neuromorphic hardware systems scale to larger and larger sizes, the communication system used to transfer information between neuromorphic elements and traditional computers must scale to keep up. In prior work, we describe the use of a separate neuromorphic array communications controller to support low-latency, high-throughput communication between our neuromorphic systems and a traditional computer. In this work, the neuromorphic array communications controller is used to support the scaling of a neuromorphic development system which uses multiple neuromorphic processors arranged in a two-dimensional array. The neuromorphic array communications controller, along with scalable local connections, is used to create a scalable neuromorphic platform to enable the development and testing of large neuromorphic network arrays.

Reservoir computing is a framework of computation designed with the intention of easing the training of recurrent neural networks. Physical implementation of these reservoirs plays a crucial role in enhancing this advantage by improving its processing speed and reducing hardware training costs. In this paper, we present a hardware architecture for efficient and compact implementation of memristor based reservoirs (liquid state machines specifically). The proposed system consists of a reconfigurable architecture such that any given reservoir topology can be implemented on it. It also consists of a memristor crossbar based readout layer that is trained using supervised spike-timing-dependent plasticity (STDP) techniques. The presented techniques are simple and require simple hardware for their implementation and hence reduce area overhead for training-in-hardware of physical reservoir computing systems.

Resistive Random Access Memory (ReRAM), a form of non-volatile memory, has been proposed as a Flash memory replacement. In addition, novel circuit architectures have been proposed that rely on newly discovered or predicted behavior of ReRAM. One such architecture is the memristive Dynamic Adaptive Neural Network Array, developed to emulate the functionality of a biological neuron system. We demonstrated ReRAM devices that show a synaptic tendency by changing their resistance in an analog fashion. The CMOS compatible nanoscale ReRAM devices shown are based on an HfO2switching layer that sits on a tungsten electrode and is covered by a titanium oxygen scavenger layer and a titanium nitride top electrode. In this work, we showed devices exceeding endurance values of 10B cycles with a discrete Roff/Ronratio of 15. Multi-level states were achieved by using consecutive ultra-short 5/1.5 ns pulses during the reset operation. A neural network simulation was performed in which the synaptic weights were perturbed with the ReRAM variability, which was extracted from two different characterization methods: (1) via direct write, and (2) via a write/read verification approach during the reset operation. A substantial improvement of the neural network fitness was demonstrated when using the write/read verification approach.

In the past decade, complementary metal oxide semiconductor-memristor hybrid neuromorphic systems have gained importance owing to the advantages of memristors such as nano-scale size, non-volatility, and low-power operation. However, they are often accompanied by non-ideal properties that can impact the system’s performance. This article presents device-aware circuit design to mitigate such effects. A bi-memristor synapse with a robust spike-timing-dependent plasticity (STDP) is designed. A mixed-mode neuron is presented whose accumulation rate is tunable on-chip and can be used with a variety of memristors without needing a re-design. The proposed designs are employed together in an example pattern recognition system. A scalable winner-takes-all circuit is presented for the output stage. A pattern recognition task based on a simple STDP-based learning is demonstrated such that the recognition rate is directly dependent on the learnt weights. Device-level issues such as switching speed/threshold asymmetry, limited switching resolution, endurance, and varying resistance range (across devices) are shown to adversely affect learning at the system level and it is demonstrated that the proposed circuits can mitigate them. Last, the area and energy costs of the proposed designs are evaluated and compared against other implementations in the literature.

Conventional digital logic operations have distinguishable power signatures. Side channel power analysis combined with classification algorithm can reveal unknown logic operations. Revealing the underlying operations is the main task in reverse engineering an application. In this paper, we propose an unconventional way of overcoming this vulnerability by using chaos based reconfigurable logic operations. The chaos gate used in this paper is built from a simple 3 transistor chaotic oscillator capable of generating aperiodic states starting from a suitably chosen initial condition. We propose a design methodology using chaos gate to implement different logic operations with very similar power profiles. Therefore, it becomes significantly harder to distinguish logical operations built with chaotic logic gates in contrast to the conventional static CMOS logic gates. In addition, we show a mixed implementation of bitwise logic operations using different proportions of chaos and conventional gates resulting in a significant reduction of total overhead.

Emerging nano-devices like memristors display stochastic switching behavior which poses a big uncertainty in their implementation as the next-generation CMOS alternative. However, this stochasticity provides an opportunity to design circuits for hardware security. There are several examples in literature where the stochastic switching time of memristors are used as the source of entropy to build true random number generators (TRNGs). Software-based pseudo-random numbers may not be random enough for many different applications where true random numbers are a necessity. In this work, we have analyzed traditional TRNG designs that utilize memristors' switching time and evaluated them in varying operating conditions and with process variation in mind. Specifically, we have mathematically formulated how large process variation and strong temperature and voltage dependence of memristors can degrade the performance of these TRNGs. Depending on these analyses, we also have proposed a new way of designing memristive TRNG based on difference between stochastic high resistance states of a pair of memristors. Using simple probabilistic mathematics, we have evaluated our proposed method with existing ones and shown that our proposed design is robust in unfavorable environmental conditions and in the presence of large process variation where traditional TRNG bit quality degrades rapidly.

Recent advances in resistive random access memory (RRAM) as high density, low power, and faster memory systems drive the need for devising a more lightweight integrity checking system for RRAM. In this paper, we design a new tag generation system for integrity checking of RRAM. A single read operation to a crossbar RRAM in the presence of sneak path currents can output a tag for the memory data that can be used for integrity checking. An analytical approach to model such a tag generation process is described in this paper. Security results predicted by the analytical model provide various design options leading to an optimal system from the perspective of considered security properties. The proposed design is simulated to investigate and verify the security properties of the system for a number of optimal design options predicted by the analytical model. Reliability of the proposed system is also measured for varying conditions of device parameters, operating temperatures, load resistances, and read voltage. Finally, the performance of the proposed system is compared against another existing lightweight tag generation method from the perspective of energy consumption, transistor count, and delay.

Resource constrained devices are the building blocks of the internet of things (IoT) era. Since the idea behind IoT is to develop an interconnected environment where the devices are tiny enough to operate with limited resources, several control systems have been built to maintain low energy and area consumption while operating as IoT edge devices. Several researchers have begun work on implementing control systems built from resource constrained devices using machine learning. However, there are many ways such devices can achieve lower power consumption and area utilization while maximizing application efficiency. Spiky neuromorphic computing (SNC) is an emerging paradigm that can be leveraged in resource constrained devices for several emerging applications. While delivering the benefits of machine learning, SNC also helps minimize power consumption. For example, low energy memory devices (memristors) are often used to achieve low power operation and also help in reducing system area. In total, we anticipate SNC will provide computational efficiency approaching that of deep learning while using low power, resource constrained devices.

Neuromorphic computing is one promising post-Moore's law era technology. In order to develop and use neuromorphic systems, traditional von Neumann-based computers must be able to communicate with neuromorphic hardware to support functionality such as monitoring the state of the network, optimizing the array to better perform the task, and input/output data processing. In this paper, we describe our use of a separate neuromorphic array communications controller to support highthroughput, low-latency communication between a traditional computer and our implementations of neuromorphic systems. The goal of the communications controller is to provide enough performance to facilitate the desired interaction between the systems and to enable scaling of the neuromorphic systems to larger sizes.

Resistive RAM (ReRAM) devices are low power, fast and reliable nanoelectronic memory devices, which have proven to be crucial in both neuromorphic hardware and memory design. Despite their utility, challenges remain in forming and programming these devices before they can be used in a system. This paper builds on a forming circuit, incorporating programming technique in the same circuit in addition to outlining a scan-in approach to programming both CMOS and ReRAM memory elements. The proposed scheme utilizes a single input pin to serially scan-in a bit sequence to program the memory elements, leveraging a digital control circuitry. The suggested protocol is applied to a neuromorphic system to configure synaptic properties to implement a spiking neural network. Lastly, the need for reduction of forming voltage is highlighted with power dissipation data from Spectre simulation.

Neuromorphic computing systems are alternatives to conventional microprocessors, often built from unconventional hardware. Designing and evaluating these systems requires multiple levels of simulation, from the device level to the circuit level to the system level. In this paper, we describe the system level simulator of a neuromorphic computing system based on memristors. We compare it to a circuit level simulator of the same system, both verifying its accuracy and demonstrating its performance improvement. We argue that system level simulation is an essential part of the design process of neuromorphic systems.

Current deep learning approaches have been very successful using convolutional neural networks trained on large graphical-processing-unit-based computers. Three limitations of this approach are that (1) they are based on a simple layered network topology, i.e., highly connected layers, without intra-layer connections; (2) the networks are manually configured to achieve optimal results, and (3) the implementation of the network model is expensive in both cost and power. In this article, we evaluate deep learning models using three different computing architectures to address these problems: quantum computing to train complex topologies, high performance computing to automatically determine network topology, and neuromorphic computing for a low-power hardware implementation. We use the MNIST dataset for our experiment, due to input size limitations of current quantum computers. Our results show the feasibility of using the three architectures in tandem to address the above deep learning limitations. We show that a quantum computer can find high quality values of intra-layer connection weights in a tractable time as the complexity of the network increases, a high performance computer can find optimal layer-based topologies, and a neuromorphic computer can represent the complex topology and weights derived from the other architectures in low power memristive hardware.

Hardware security has emerged as a field concerned with issues such as integrated circuit (IC) counterfeiting, cloning, piracy, and reverse engineering. Physical unclonable functions (PUF) are hardware security primitives useful for mitigating such issues by providing hardware-specific fingerprints based on intrinsic process variations within individual IC implementations. As technology scaling progresses further into the nanometer region, emerging nanoelectronic technologies, such as memristors or RRAMs (resistive random-access memory), have become interesting options for emerging computing systems. In this article, using a comprehensive temperature dependent model of an HfO x (hafnium-oxide) memristor, based on experimental measurements, we explore the best region of operation for a memristive crossbar PUF (XbarPUF). The design considered also employs XORing and a column shuffling technique to improve reliability and resilience to machine learning attacks. We present a detailed analysis for the noise margin and discuss the scalability of the XbarPUF structure. Finally, we present results for estimates of area, power, and delay alongside security performance metrics to analyze the strengths and weaknesses of the XbarPUF. Our XbarPUF exhibits nearly ideal (near 50%) uniqueness, bit-aliasing and uniformity, good reliability of 90% and up (with 100% being ideal), a very small footprint, and low average power consumption ≈104μW.

Memristors are widely leveraged in neuromorphic systems for constructing synapses. Resistance switching characteristics of memristors enable online learning in synapses. This paper addresses a fundamental issue associated with the design of synapses with memristors whose switching rates in either direction differ up to two orders of magnitude. A twin-memristor synapse that uses memristors with identical switching rates is first presented. It is shown this design fails in the case of disproportionate switching times. To circumvent this issue, a quad-memristor synapse is also considered. The scheme used for online learning of the synapse circuit implementation, and simulation results are also presented. To compare the two synapses, their area, clock frequency, dynamic power and energy per spike values are provided.

This paper proposes a practical polynomial model for HfO2memristor fabricated in-house at SUNY Polytechnic Institute. Although there is no shortage of memristor models in the literature, most models are not general and assume specific switching and conduction mechanisms. This is often deemed impractical for circuit designers who wish to develop a model for a specific technology of interest. Thus, circuit designers have sought empirical models that are easily fit to their specific device. The model should be simple, intuitive, and most importantly, fast to converge. The proposed model is based on measurable parameters and matches the experimental data well. The convergence of our model is tested against other models in the literature and shows comparable results. It is also shown that the smoothness of the model around the memristor threshold is critical for fast convergence time.

The internet of things (IoT) is quickly emerging as the next major domain for embedded computer systems. Although the term IoT could be defined in a variety of different ways, IoT always encompasses typically ordinary devices (e.g., thermostats and kitchen appliances) augmented with computational power that allows regular communication via the internet. Given the simplicity of typical IoT devices, their on-board computer systems must also be simple in the sense that they be small and consume minimal power. However, the IoT itself presents new privacy and security concerns that must be considered when designing IoT devices. In order to provide robust security with minimal area and power overhead, it is the premise of this paper that IoT security be implemented using nanoelectronic security primitives and nano-enabled security protocols. Such nanoscale security primitives are expected to utilize a very small amount of area and consume a negligible amount of power, all while providing the required levels of security. This paper presents some examples of nanoelectronic security primitives and discusses how such circuits and systems can be of use for inclusion in emerging IoT devices.

Dynamic Adaptive Neural Network Arrays (DANNAs) are neuromorphic computing systems developed as a hardware based approach to the implementation of neural networks. They feature highly adaptive and programmable structural elements, which model artificial neural networks with spiking behavior. We design them to solve problems using evolutionary optimization. In this paper, we highlight the current hardware and software implementations of DANNA, including their features, functionalities and performance. We then describe the development of an Application Development Platform (ADP) to support efficient application implementation and testing of DANNA based solutions. We conclude with future directions.

Physical unclonable functions (PUF) provide a hardware specific unique signature or finger print for an integrated circuit that can be leveraged to mitigate several security vulnerabilities. A dense memristive crossbar PUF is described which utilizes variations in the write-time of memristors as the primary entropy source. For this work, the write-time varies according to six specific device parameters which can be directly measured from fabricated memristors and easily included in an accurate model for circuit simulation. The results presented show strong statistical performance for the proposed design in terms of entropy, uniqueness and uniformity. Furthermore, the nature of sneak path currents in the crossbar structure are leveraged to provide an exponential number of unique configurations for each response bit. Results also show that the proposed crossbar-based PUF provides improved power consumption and smaller area utilization when compared to CMOS-based and other nanoelectronic PUF circuits.

Information security has emerged as an important system and application metric. Classical security solutions use algorithmic mechanisms that address a small subset of emerging security requirements, often at high-energy and performance overhead. Further, emerging side-channel and physical attacks can compromise classical security solutions. Hardware security solutions overcome many of these limitations with less energy and performance overhead. Nanoelectronics-based hardware security preserves these advantages while enabling conceptually new security primitives and applications. This tutorial paper shows how one can develop hardware security primitives by exploiting the unique characteristics such as complex device and system models, bidirectional operation, and nonvolatility of emerging nanoelectronic devices. This paper then explains the security capabilities of several emerging nanoelectronic devices: memristors, resistive random-access memory, contact-resistive random-access memory, phase change memories, spin torque-transfer random-access memory, orthogonal spin transfer random access memory, graphene, carbon nanotubes, silicon nanowire field-effect transistors, and nanoelectronic mechanical switches. Further, the paper describes hardware security primitives for authentication, key generation, data encryption, device identification, digital forensics, tamper detection, and thwarting reverse engineering. Finally, the paper summarizes the outstanding challenges in using emerging nanoelectronic devices for security.

Memristors are being explored for a wide variety of applications such as neuromorphic computing, memory and digital logic. However, they suffer from process variations like any other nanodevice, which in turn impacts their applicability. The effect of process variations, specifically variation in thickness, is highly non-linear on memristors; the effect is greater near the lower memristance region (near M$_{\rm on}$) than in the higher memristance region (near M$_{\rm off}$). Due to this non-linear effect, many applications do not use the lower memristance values. Consequently, the application's functionality and performance is affected. In this work, we propose a technique called parallel memristors. In this technique, instead of using a single memristor, the application uses several memristors connected in parallel. Each memristor in this parallel structure is programmed to a higher memristance value to tolerate variations. Since many memristors are connected in parallel, the effective memristance value can be near the M$_{\rm on}$value, thereby achieving high-speed operation. We evaluate the parallel memristor technique in two different applications—memristor-based threshold logic and memristor-based memory. We also perform various optimizations to tradeoff between variation tolerance, power, delay, and area.

Globalization of the integrated circuit (IC) design industry is making it easy for rogue elements in the supply chain to pirate ICs, overbuild ICs, and insert hardware Trojans. Due to supply chain attacks, the IC industry is losing approximately $4 billion annually. One way to protect ICs from these attacks is to encrypt the design by inserting additional gates such that correct outputs are produced only when specific inputs are applied to these gates. The state-of-the-art logic encryption technique inserts gates randomly into the design, but does not necessarily ensure that wrong keys corrupt the outputs. Our technique ensures that wrong keys corrupt the outputs. We relate logic encryption to fault propagation analysis in IC testing and develop a fault analysis-based logic encryption technique. This technique enables a designer to controllably corrupt the outputs. Specifically, to maximize the ambiguity for an attacker, this technique targets 50% Hamming distance between the correct and wrong outputs (ideal case) when a wrong key is applied. Furthermore, this 50% Hamming distance target is achieved using a smaller number of additional gates when compared to random logic encryption.

By mimicking the highly parallel biological systems, neuromorphic hardware provides the capability of information processing within a compact and energy-efficient platform. However, traditional Von Neumann architecture and the limited signal connections have severely constrained the scalability and performance of such hardware implementations. Recently, many research efforts have been investigated in utilizing the latest discovered memristors in neuromorphic systems due to the similarity of memristors to biological synapses. In this paper, we explore the potential of a memristor crossbar array that functions as an autoassociative memory and apply it to brain-state-in-a-box (BSB) neural networks. Especially, the recall and training functions of a multianswer character recognition process based on the BSB model are studied. The robustness of the BSB circuit is analyzed and evaluated based on extensive Monte Carlo simulations, considering input defects, process variations, and electrical fluctuations. The results show that the hardware-based training scheme proposed in the paper can alleviate and even cancel out the majority of the noise issue.

Hardware security has emerged as an important field of study aimed at mitigating issues such as piracy, counterfeiting, and side channel attacks. One popular solution for such hardware security attacks are physical unclonable functions (PUF) which provide a hardware specific unique signature or identification. The uniqueness of a PUF depends on intrinsic process variations within individual integrated circuits. As process variations become more prevalent due to technology scaling into the nanometer regime, novel nanoelectronic technologies such as memristors become viable options for improved security in emerging integrated circuits. In this paper, we provide an overview of memristor based PUF structures and circuits that illustrate the potential for nanoelectronic hardware security solutions.

In this work, we propose a hardware realization of the Brain-State-in-a-Box (BSB) neural network model training algorithm. This method can be implemented as an analog/digital mixed-signal circuit to train memristor crossbar arrays within BSB circuits. The training effect is demonstrated through experimentation and the quality as an auto-associative memory is also analyzed and compared with software based training methods. The impacts of non-ideal device characteristics and fabrication defects in crossbar arrays are discussed. Our hardware architecture shows great potential for low power, high speed, small hardware size computations, and provides inherent security features.

Hardware security has emerged as an important field of study aimed at mitigating issues such as piracy, counterfeiting, and side channel attacks. One popular solution for such hardware security attacks are physical unclonable functions (PUF) which provide a hardware specific unique signature or identification. The uniqueness of a PUF depends on intrinsic process variations within individual integrated circuits. As process variations become more prevalent due to technology scaling into the nanometer regime, novel nanoelectronic technologies such as memristors become viable options for improved security in emerging integrated circuits. In this paper, we describe a novel memristive PUF (M-PUF) architecture that utilizes variations in the write-time of a memristor as an entropy source. The results presented show strong statistical performance for the M-PUF in terms of uniqueness, uniformity, and bit-aliasing. Additionally, nanoscale M-PUFs are shown to exhibit reduced area utilization as compared to CMOS counterparts.

Neural logic blocks (NLBs) enable the realization of biologically inspired reconfigurable hardware. Networks of NLBs can be trained to perform complex computations such as multilevel Boolean logic and optical character recognition (OCR) in an area- and energy-efficient manner. Recently, several groups have proposed perceptron-based NLB designs with thin-film memristor synapses. These designs are implemented using a static threshold activation function, limiting the set of learnable functions to be linearly separable. In this work, we propose two NLB designs-robust adaptive NLB (RANLB) and multithreshold NLB (MTNLB)-which overcome this limitation by allowing the effective activation function to be adapted during the training process. Consequently, both designs enable any logic function to be implemented in a single-layer NLB network. The proposed NLBs are designed, simulated, and trained to implement ISCAS-85 benchmark circuits, as well as OCR. The MTNLB achieves 90 percent improvement in the energy delay product (EDP) over lookup table (LUT)-based implementations of the ISCAS-85 benchmarks and up to a 99 percent improvement over a previous NLB implementation. As a compromise, the RANLB provides a smaller EDP improvement, but has an average training time of only ≈ 4 cycles for 4-input logic functions, compared to the MTNLBs ≈ 8-cycle average training time.

The Brain-State-in-a-Box (BSB) model is an auto-associative neural network that has been widely used in optical character recognition and image processing. Traditionally, the BSB model was realized at software level and carried out on high-performance computing clusters. To improve computation efficiency and reduce resources requirement, we propose a hardware realization by utilizing memristor crossbar arrays. In this work, we explore the potential of a memristor crossbar array as an auto-associative memory. More specificly, the recall function of a multi-answer character recognition based on BSB model was realized. The robustness of the proposed BSB circuit was analyzed and evaluated based on massive Monte-Carlo simulations, considering input defects, process variations, and electrical fluctuations. The physical constrains when implementing a neural network with memristor crossbar array have also been discussed. Our results show that the BSB circuit has a high tolerance to random noise. Comparably, the correlations between memristor arrays introduces directional noise and hence dominates the quality of circuits.

The Brain-State-in-a-Box (BSB) model is an auto-associative neural network that has been widely used in optical character recognition and image processing. Traditionally, the BSB model was realized at software level and carried out on high-performance computing clusters. To improve computation efficiency and reduce resource requirement, we propose a hardware realization by utilizing memristor crossbar arrays. Memristors can remember the historical profiles of the excitations and record them as analog variables. The similarity to biological synaptic behavior has encouraged a lot of research on memristor-based neuromorphic hardware system. In this work, we explore the potential of a memristor crossbar array as an auto-associative memory. More specifically, the recall function of a multi-answer character recognition based on BSB model was realized. The robustness of the proposed BSB circuit was analyzed and evaluated based on massive Monte-Carlo simulations, considering input defects, process variations, and electrical fluctuations. The physical constraints when implementing a neural network with memristor crossbar array have also been discussed. Our results show that the BSB circuit has a high tolerance to random noise. Comparably, the correlations between memristor arrays introduce directional noise and hence dominate the quality of the circuit.

With technology migration into nano and molecular scales several hybrid CMOS/nano logic and memory architectures have been proposed that aim to achieve high device density with low power consumption. The discovery of the memristor has further enabled the realization of denser nanoscale logic and memory systems by facilitating the implementation of multilevel logic. This work describes the design of such a multilevel nonvolatile memristor memory system, and the design constraints imposed in the realization of such a memory. In particular, the limitations on load, bank size, number of bits achievable per device, placed by the required noise margin for accurately reading and writing the data stored in a device are analyzed. Also analyzed are the nondisruptive read and write methodologies for the hybrid multilevel memristor memory to program and read the memristive information without corrupting it. This work showcases two write methodologies that leverage the best traits of memristors when used in either linear (low power) or nonlinear drift (fast speeds) modes. The system can therefore be tailored depending on the required performance parameters of a given application for a fast memory or a slower but very energy-efficient system. We propose for the first time, a hybrid memory that aims to incorporate the area advantage provided by the utilization of multilevel logic and nanoscale memristive devices in conjunction with CMOS for the realization of a high density nonvolatile multilevel memory.

The recent emergence of the memristor has led to a great deal of research into the potential uses of the devices. Specifically, the innate reconfigurability of memristors can be exploited for applications ranging from multilevel memory, programmable logic, and neuromorphic computing, to name a few. In this work, memristors are explored for their potential use in dense programmable logic circuits. While much of the work is focused on Boolean logic, nontraditional styles including threshold logic and neuromorhpic computing are also considered. In addition to an analysis of the circuits themselves, computer-aided design (CAD) flows are presented which have been used to map digital logic functionality to dense complementary metal-oxide-semiconductor (CMOS)-memristive logic arrays. As exemplified through the circuits described here memristor-based digital logic holds great potential for high-density and energy-efficient computing.

Researchers have claimed that the memristor, the fourth fundamental circuit element, can be used for computing. In this work, we utilize memristors as weights in the realization of low-power Field Programmable Gate Arrays (FPGAs) using threshold logic which is necessary not only for low power embedded systems, but also realizing biological applications using threshold logic. Boolean functions, which are subsets of threshold functions, can be implemented using the proposed Memristive Threshold Logic (MTL) gate, whose functionality can be configured by changing the weights (memristance). A CAD framework is also developed to map the weights of a threshold gate to corresponding memristance values and synthesize logic circuits using MTL gates. Performance of the MTL gates at the circuit and logic levels is also evaluated using this CAD framework using ISCAS-85 combinational benchmarking circuits. This work also provides solutions based on device options and refreshing memristance, against drift in memristance, which can be a potential problem during operation. Comparisons with the existing CMOS look-up-table (LUT) and capacitor threshold logic (CTL) gates show that MTL gates exhibit less energy-delay product by at least 90 percent.

As conventional CMOS technology approaches fundamental scaling limits novel nanotechnologies offer great promise for VLSI integration at nanometer scales. The memristor, or memory resistor, is a novel nanoelectronic device that holds great promise for continued scaling for emerging applications. Memristor behavior is very similar to that of the synapses necessary for realizing a neural network. In this research, we have considered circuits that leverage memristance in the realization of an artificial synapse that can be used to implement neuromorphic computing hardware. A charge sharing based neural network is described which consists of a hybrid of conventional CMOS technology and novel memristors. Results demonstrate that the circuit can be implemented with energy consumption on the order of tens of femto-joules. Furthermore, a training circuit is presented for implementing supervised learning in hardware with low area overhead.

With technology scaling and 3D integration, it is becoming possible to accommodate hundreds of processing elements forming many-core chip multiprocessors (CMP). Manual floorplanning of chips becomes more time consuming and inefficient as complexity increases. Compared to traditional ASIC architectures, CMPs have homogenous processing elements and regular network topologies. In this paper, we propose a floorplan technique that can exploit the regularity and structure present in 3D-CMP networks. We can generate floorplans for different topologies under different design constraints. Compared with traditional floorplanning approaches, our tool shows significant advantages in reducing the total interconnect wire-length and power.

Technology migration into nano and molecular scales has led to the design of several hybrid CMOS/nano logic and memory architectures that aim to achieve high device density with low power consumption. The discovery of the memristor has further enabled the realization of denser nanoscale memory and logic systems by facilitating the implementation of multi-level logic. In this work we propose a sneak-path free memory architecture, the 1T1M (1 transistor per memristor) that provides for 2-bit storage in each data cell (memristor). Robust read and write methodologies for the proposed architecture are also discussed and tradeoffs between faster write speeds and larger read noise margins are also analyzed. Another highlight of this work is the usage of the exponential drift memristor model to further enhance write speeds of these devices which are otherwise much slower.

Memristors are employed by a wide variety of applications such as neural networks, memory and digital logic. However, the process variation effects of memristors may affect these applications. In this research, we consider the effect of process variations in the thickness of the oxide layer of memristors that are used in Memristor-based Threshold Logic (MTL) gates. As the effect of variations is less pronounced in high memristance values, a variation tolerant design without any degradation in speed is achieved by having a number of high memristance devices in parallel (redundancy factor). We propose an algorithm for the MTL gates to determine the number of memristors in parallel and the variation-minimal high memristance state. A power optimization algorithm is also proposed to map gates in a design using different libraries that have different performance characteristics. Finally, we present the power, delay performance and also the redundancy factor of memristors for various benchmark circuits.

As conventional CMOS technology approaches fundamental scaling limits novel nanotechnologies offer great promise for VLSI integration at nanometer scales. The memristor, or memory resistor, is a novel nanoelectronic device that holds great promise for continued scaling for emerging applications. Memristor behavior is very similar to that of the synapses necessary for realizing a neural network. In this research, we have considered circuits that leverage memristance in the realization of an artificial synapse that can be used to implement neuromorphic computing hardware. A novel charge sharing based neural network is described which consists of a hybrid of conventional CMOS technology and novel memristors. Simulation results are presented which demonstrate that dense CMOS-memristive neural networks can be implemented with energy consumption on the order of tens of femto-joules.

No abstract available.

With technology migration into nano and molecular scales several hybrid CMOS/nano logic and memory architectures have been proposed thus far that aim to achieve high device density with low power consumption. The discovery of the memristor has further enabled the realization of denser nanoscale logic and memory systems. This work describes the design of such a multilevel memristor memory (MLMM) system, and the design constraints imposed in the realization of such a memory. In particular, the limitations on load, bank size, number of bits achievable per device, placed by the required noise margin (NM) for accurately reading the data stored in a device are analyzed.

With conventional CMOS technology approaching fundamental scaling limits, novel nanotechnologies offer great promise for VLSI integration at nanometer scales. The memristor, or "memory resistor," is a novel nanoelectronic device that holds great promise for emerging VLSI applications. Essentially, a memristor is a programmable resistor whose resistance is altered based on specified toggle conditions. Furthermore, memristors are non-volatile such that the state of the device remains until the next toggle condition. This paper will provide an overview of memristors and memristive systems with a particular focus on applications for emerging VLSI circuits and systems. Examples of memristor based memory and logic circuits are to be discussed in detail including device modeling, memristor memory analysis, and memristor based logic. While the examples shown are focused on digital applications, memristors also hold great promise for analog, mixed signal and biomedical systems. These several potential applications will be discussed as part of this overview.

Along with the emergence of complex VLSI technologies such as multiple processor systems on chips (MPSOC), several challenges exist including increased defects, power consumption, and thermal effects. This paper focuses on how to mitigate thermal effects using a temperature sensitive thermal sensor. The here is to design a thermal sensor which is highly sensitive to the temperature. Such an on-chip sensor could be used to drive a management system for regulating on-chip temperature. The particular thermal sensor presented in this paper is built around a dual-MOSFET equivalent resistor. As is shown in this work, this thermal sensor provides improved temperature sensitivity when compared to alternatives.

In recent years, novel nanotechnology has been considered as an eventual replacement or extension for conventional technologies (e.g., CMOS) as they migrate to smaller scales. This work explores the use of such nanoscale devices for the development of a robust hybrid CMOS-nano field programmable gate array (FPGA). In particular, we utilize the properties of negative differential resistance (NDR) and hysteretic switching, observed from some nanoelectronic devices, in the design of an array-based logic circuit dubbed the programmable majority logic array (PMLA). The hybrid CMOS-nano FPGA system design described in this paper incorporates the area and power efficiency of the nano PMLA with the speed and robustness of CMOS. Furthermore, the effects of how logic is partitioned between the nano PMLA and CMOS are also considered.

Recent research into molecular scale electronics has led to the realization of novel nanoscale devices that can be used to implement circuits such as what we dub Programmable Majority Logic Arrays (PMLA). A PMLA leverages two characteristics found in molecular electronic devices, hysteretic switching and negative differential resistance (NDR), in the implementation of a PLA based on majority logic. This paper deals with the integration of several nanoscale PMLA units with micro scale technologies to implement a high density FPGA architecture. One of the key contributions of this work is the interface between the top nanoscale layer and a lower CMOS layer. Two approaches are considered for interfacing these two technologies: (1) direct connection and (2) connection utilizing tapered buffers between the layers for improved delay. The intermediate tapered buffers in the second approach ensure that the variation in feature size, and hence load capacitance, from one layer to the next is not too substantial. This paper also demonstrates the potential of the PMLA FPGA from a high level perspective in terms of increased density and performance for a set of applications.

The focus of the field of molecular electronics in recent years has been mostly limited to the development of molecular electronic test devices and the characterization of electron transport through organic molecules. However, in order for molecular electronic technology to be realized, it is probable that these devices will have to first be integrated with traditional CMOS components and circuits. For this reason, we present the design of a molecular device/CMOS hybrid circuit that exemplifies how the two technologies can be integrated as well as how the CMOS circuitry can be used for the on-chip characterization of the molecular electronic devices. This work includes: the fabrication and characterization of a silicon-based CMOS-compatible molecular electronic device, the design of a hybrid circuit that can be used for on-chip characterization of the molecular devices, and simulations based upon the actual experimental device results that verify the effectiveness of the circuit. The components in this preliminary work have been limited to simple example devices and circuits to serve as a proof of concept, but the basic framework can be expanded in the future to include much more complex behaviors and systems.

In recent years, many advances have been made in the development of molecular scale devices. Experimental data shows that these devices have potential for use in both memory and logic. This article describes the challenges faced in building crossbar array-based molecular memory and develops a methodology to optimize molecular scale architectures based on experimental device data taken at room temperature. In particular, issues in reading and writing such as memory using CMOS are discussed, and a solution is introduced for easily reading device conductivity states (typically characterized by very small currents). Additionally, a metric is derived to determine the voltages for writing to the crossbar array. The proposed memory design is also simulated with consideration to device parameter variations. Thus, the results presented here shed light on important design choices to be made at multiple abstraction levels, from devices to architectures. Simulation results, incorporating experimental device data, are presented using Cadence Spectre.

We present a computer architecture design that utilizes molecular electronic devices fabricated from self-assembled monolayers (SAM) of molecules. This architecture has been designed for a process being developed at the University of Virginia where molecules are assembled via vapor phase deposition. As this process lends itself nicely to developing multiple layers of devices on a single substrate, the circuit and architectural designs presented here exist in three dimensions. Through this work we show how molecular electronics naturally allows for 3D integration at the nanoscale.The design consists of two types of molecular devices: switches with memory and resonant tunneling diodes (RTD). These switching molecules are patterned between layers of metal to form a uniform crossbar array that can behave similar to a programmable logic array (PLA). In this design, the crossbar arrays drive rows of circuits, referred to as Goto pairs, consisting of two stacked molecular RTDs. As described in previous work, a Goto pair with only one resistor driving its input functions as a latch whereas the circuit acts as a majority gate when driven by multiple resistors. Since the crossbar arrays can be programmed such that the various Goto pairs are driven by different numbers of inputs, the overall circuit has the ability to implement logic as networks of latches and majority gates. Using crossbar arrays in this way is somewhat different from other approaches in that logic is not simply implemented in the array but is a product of both the array and the Goto pair functionality.

In recent years many advances have been made in the development of molecular scale devices. Experimental data shows that these devices have potential for use in both memory and logic. This paper describes the challenges faced in building crossbar array based molecular memory, and develops a methodology to optimize molecular scale architectures based on experimental device data taken at room temperature. In particular, we discuss reading and writing such memory using CMOS and compiling a solution for easily reading device conductivity states (typically characterized by very small currents). Additionally, a metric is derived to determine the voltages for writing to the crossbar array. Simulation results, incorporating experimental device data, are presented using Cadence Spectre.

As the nanoelectronics field reaches the maturity needed for circuit-level integration, modeling approaches are needed that can capture nonclassical behaviors in a compact manner. This paper proposes a universal device model (UDM) for two-terminal devices that addresses the challenge of correctly balancing accuracy, complexity, and flexibility. The UDM qualitatively captures fundamental classical and quantum phenomena and enables nanoelectronic circuit design and simulation. We discuss the motivation behind this modeling approach as well as the underlying details of the model. Furthermore, we present a circuit example of the model in action.