Multithreaded architectures have the ability to tolerate long memory latencies and unpredictable synchronization delays. We propose a multithreaded architecture that is capable of exploiting both coarse-grain parallelism, and fine-grain instruction level parallelism in a program. Instruction-level parallelism is exploited by grouping instructions from a number of active threads at runtime. The architecture supports multiple resident activations to improve the extent of locality exploited. Further, a distributed data structure cache organization is proposed to reduce both the network: traffic and the latency in accessing remote locations. Initial performance evaluation using discrete-event simulation indicates that the architecture is capable of achieving very high processor throughput. The introduction of the data structure cache reduces the network latency significantly. The impact of various cache organizations on the performance of the architecture is also discussed in this paper.>

The main challenge in the field of Very Large Instruction Word (VLIW) and superscalar architectures is ezploiting as much instruction-level parallelism as possible. In this paper an ezecution model which uses multiple instruction sequences and eztracts instruction-level parallelism at runtime from a set of enabled threads has been presented. A new multi-ring architecture has been proposed to support the ezeculion model. The multithreaded architecture features (i) large resident activations to improve program and data locality, (ii) a novel high-speed buger organization which ensures zero load/store stalls for the local variables of an activation, and (iii) a dynamic instruction scheduler that groups operations from multiple threads for ezecution. Initial performance evaluation studies predict that the proposed architecture is capable of ezecuting 7 concurrent operations per cycle with 8 ezecution pipes and 6 rings.