We propose an automatic wafer defect maps detection method based on unsupervised learning. There is no need for human labeling, and similar defect clusters are identified automatically without human intervention. As a result, the process is less error-prone. Whenever the wafer test result of a WUT is available, it can be compared immediately with existing clusters. If the wafer map matches one of the known defect patterns, then RCA can be done efficiently.

Wafer map defect pattern recognition is valuable for root cause analysis and yield learning. Most of the previous studies on defect pattern recognition are based on supervised machine learning, in which labeled wafer maps are used to train a machine learning model for automatic classification. Some problems arise in this approach. First, there may be misclassification in the original labeled data, which makes it difficult to establish an accurate prediction model. Secondly, defect patterns that are not defined before will not be classified correctly. In this paper, we proposed a semi-supervised framework to deal with these problems. Labeled wafer maps are first used to train a prediction model, with likely misclassified data excluded. The prediction model is then used to classify unlabeled data. The remaining data that cannot be properly classified are then sent to an unsupervised learning algorithm to extract more defect patterns with enhanced labeling techniques. This proposed approach is validated with TSMC 811K database, in which we are able to define five new defect pattern types. Experimental results show that total 14 defect types can be recognized with overall accuracy of 94.37%.

Wafer defect maps provide precious information of fabrication and test process defects, so they can be used as valuable sources to improve fabrication and test yield. This paper applies artificial intelligence based pattern recognition techniques to distinguish fab-induced defects from test-induced ones. As a result, test quality, reliability and yield could be improved accordingly. Wafer test data contain site-dependent information regarding test configurations in automatic test equipment, including effective load push force, gap between probe and load-board, probe tip size, probe-cleaning stress, etc. Our method analyzes both the test paths and site-dependent test characteristics to identify test-induced defects. Experimental results achieve 96.83% prediction accuracy of six NXP products, which show that our methods are both effective and efficient.

This study aims to exploit an integrated-circuit (IC) testing model based on a statistical simulation method to evaluate the test yield and quality of IC products. Using normal probability distributions of product properties, we digitally analyzed IC yield and quality, introduced testing threshold and guardband, and assessed various parameters' influence on outcomes. Because future manufacturing speed is unpredictable, we used current manufacturing technology and existing-product electrical properties to estimate future product-distribution trends. Since the progress of developmental improvements for testing technologies has been slow, it has become a greater challenge for a supplier to determine the use of existing instruments and tools to achieve quality products with near-zero defects. To improve product quality, a new scheme of Multiple tests has been proposed. Moreover, we used a set of parameters from the International Technology Roadmap for Semiconductors (ITRS) to demonstrate the proposed Multiple testing, and to show that the test yield can be improved while attaining the desired quality.

Wafer test integrates innovative works from upstream, automatic test equipment (ATE); middle stream, 2.3D/2.5D; and downstream, statistical analysis of randomness on wafer pattern recognition. NXP Taiwan proposes an AI-driven yield prediction of ATE to reduce test cost during frequent modification and changes in test systems. SiPlus proposes competitive 2.3D and SiPlus eHDF to compare many metrics with 2.5D interposer technology. Powertech Technology Inc. focuses the statistical analysis of randomness on conventional spatial wafer defect patterns. This session addresses an integrated innovation along test systems in ATE in upstream, then 2.3D/SiPlus eHDF integration structure design, finally novel randomness effects on wafer defect diagnosis.

For very deep sub-micrometer VLSI, crosstalk becomes an important issue in affecting performance and signal integrity of the circuits. Two crosstalk fault effects, namely, glitch and crosstalk-induced delay, in the system-on-chip (SOC) interconnect bus are analyzed and a unified scheme to detect them is proposed and demonstrated in this paper. The crosstalk induced delay is found to be superposition of the induced glitch and the applied signal at the victim line, and this effect is more important in affecting the circuit performance. A pulse detector with an adjustable detection threshold is proposed to detect glitches and consequently the induced delay. Several issues affecting the yield of the proposed testing scheme are discussed and Monte Carlo simulations are conducted to show the feasibility of the scheme.

We propose a multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two major issues are addressed. 1) The oscillation ring test (ORT) and its diagnosis scheme for interconnects based on the popular IEEE Standard 1500 are integrated into the multilevel routing framework to achieve testability enhancement. We augment the traditional multilevel framework of coarsening and uncoarsening by introducing a preprocessing stage that analyzes the interconnect structure for better resource estimation before the coarsening stage, and a final stage after uncoarsening that improves testability to achieve 100% interconnect fault coverage and maximal diagnosability. 2) We present a heuristic to reduce routing congestion to optimize the multiple-fault probability, chemical-mechanical polishing- and optical proximity correction-induced manufacturability, and crosstalk effects, for yield improvement. Experimental results on the Microelectronics Center for North Carolina benchmark circuits show that the proposed ORT method achieves 100% fault coverage and the optimal diagnosis resolution for interconnects. Further, the multilevel routing algorithm effectively balances the routing density to achieve 100% routing completion.

We propose an interconnect diagnosis scheme based on oscillation ring test methodology for SOC design with heterogeneous cores. The target fault models are delay faults and crosstalk glitches. We analyze the diagnosability of an interconnect structure and propose a fast diagnosability checking algorithm and an efficient diagnosis ring generation algorithm which achieves the optimal diagnosability. Two optimization techniques improve the efficiency and effectiveness of interconnect diagnosis. In all experiments, our method achieves 100% fault coverage and the optimal diagnosis resolution.

The random-like filling strategy pursuing high compression for scan test introduces large test power. To pursue high compression in conjunction with reducing test power for multiple scan chain designs is even harder and very few works were dedicated to solve this problem. This paper proposes and demonstrates a multilayer data copy (MDC) scheme for test compression as well as test power reduction for multiple scan designs. The scheme utilizes a buffer, which supports fast load using previous loaded data, to achieve test data compression and test power reduction at the same time. The scheme can be applied ATPG-independently or to be incorporated in an ATPG to generate highly compressible and power efficient test sets. Experiment results on benchmarks show that test sets generated by the scheme had large compression and power saving with little area design overhead

An interconnect diagnosis scheme based on the oscillation ring (OR) test methodology for systems-on-chip (SOC) design with heterogeneous cores is proposed. In addition to traditional stuck-at and open faults, the OR test can also detect and diagnose important interconnect faults such as delay faults and crosstalk glitches. The large number of test rings in the SOC design, however, significantly complicates the interconnect diagnosis problem. In this paper, the diagnosability of an interconnect structure is first analyzed then a fast diagnosability checking algorithm and an efficient diagnosis ring generation algorithm are proposed. It is shown in this paper that the generation algorithm achieves the maximum diagnosability for any interconnect. Two optimization techniques are also proposed, an adaptive and a concurrent diagnosis method, to improve the efficiency and effectiveness of interconnect diagnosis. Experiments on the MCNC benchmark circuits show the effectiveness of the proposed diagnosis algorithms. In all experiments, the method achieves 100% fault detection coverage and the optimal interconnect diagnosis resolution

We propose a novel oscillation ring (OR) test architecture for testing interconnects in SoC. In addition to stuck-at and open faults, this scheme can detect delay faults and crosstalk glitches. IEEE P1500 wrapper cells are modified. An efficient ring-generation algorithm is proposed to construct ORs based on a graph model. Experimental results on MCNC benchmark circuits show the feasibility of the scheme and the effectiveness of the algorithm. Our method achieves 100% fault coverage with a small number of tests.

In this paper, we propose an oscillation-based test methodology for sequential testing. This approach provides many advantages over traditional methods. (1) It is at-speed testing, which makes delay-inducing defects detectable. (2) The ATPG is much easier, and the test set is usually smaller. (3) There is no need to store output responses, which greatly reduces the communication bandwidth between the Automatic Test Equipment (ATE) and Circuit under Test (CUT). We provide a register design that supports the oscillation test, and give an effective algorithm for oscillation test generation. Experimental results on MCNC benchmarks show that the proposed test method achieves high fault coverage with smaller number of test vectors.

For the scan design, the circuit under test (CUT) in the test mode usually has larger switching activity than in the function mode, causing excessive power dissipation. In this paper, we propose a new Scan Matrix (SM) architecture for the scan-based design to achieve low power testing. The scan flip-flops are connected in a matrix style for test and its addressing is controlled by two ring generators during pattern scanning in. Unlike the traditional scan, for which scan-in data need to pass through a long path and many scan flip-flops switch simultaneously, the proposed approach dynamically forms a low-power scan path to reduce test energy and peak power during shift significantly. The architecture is scalable for large designs and has minimal circuit performance penalty. Experimental results show that, for some larger designs, nearly 99% power savings have been achieved.

Scan test for SoC has now suffered large data volume and test application time. In this paper, we propose and demonstrate an Adaptive Encoding scheme to reduce the test volume and test time for SoC scan test. The scheme, instead of handling test data themselves, encodes them in "packets" according to difference bits of two consecutive test patterns. A decoder machine is designed to decode the compressed data and a repeat filling mechanism from the ATE is adopted to eliminate the synchronization problem. It supports variable block size and is flexible in encoding multi-core test patterns; therefore, the proposed method is effective in SoC scan test. Experimental results show that on average the scheme achieves 73% reduction in test data and more than 16 times of speedup in test application time.

In this paper, we propose a BIST scheme for the digital-to-analog converter (DAC). For the scheme, an analog summer is employed and the tested signal is transformed into a timing signal for a more precise measurement. Also, a calibration circuit is added to calibrate analog imperfection to increase accuracy of the BIST circuit. An 8-bit DAC BIST circuit is designed for demonstration.

The crosstalk fault effects in deep sub-micron VLSI, namely, glitches and the crosstalk-induced delay, are investigated. The origin of their occurrence, relationship and importance in circuit operation are elucidated. It is shown that the crosstalk-induced delay is only superposition of the induced glitch with the original signal delay on the affected victim line; and crosstalk-induced delay is more important in affecting the circuit performance, and should be considered in more details for testing. A scheme which is to detect both types of faults in a unified way by just detecting glitches is proposed and studied, considering the manufacture process variation. In this way, detection of crosstalk-induced faults becomes much easier.

A test scheme for crosstalk faults, based on an oscillation signal, is proposed. It uses an oscillation signal applied to an affecting line and detects induced pulses on a victim line if a crosstalk fault exists between these two lines. It is simple and eliminates the complicated timing issues during test generation for crosstalk faults in conventional approaches. The test generation and fault simulation based on the scheme are described. Experimental results are also presented to show the described test generation procedure is effective in generating test patterns for this scheme.

This paper presents a test and diagnosis scheme for feedback type of linear analog circuits with minimal added circuits. For testing, the scheme transforms the circuit-under-test (CUT) into an oscillation circuit by (1) increasing the loop gain of the circuit, and/or (2) reconfiguring the circuit through selectively powering-off operational amplifiers (OP) of the circuit. This eliminates the need of added global paths as in the conventional oscillation test scheme. For diagnosis, the scheme transforms the circuit into a Schmitt trigger type of circuit with a positive-feedback. The output of the circuit under an applied triangular input gives signatures which are used to identify faults. Benchmark circuits have been applied with this scheme and results show that it is very effective for testing and diagnosing the feedback type of linear analog circuit.

The chips with defects, which escape the test, will cause quality problems, damage the goodwill and decline the revenue. It is important to look for a set of effective and efficient tests in the production line. In this paper, a case study of SDRAM (Synchronous DRAM)/SGRAM (Synchronous Graphics RAM) is used to demonstrate the guardband determination of testing the off-state and junction leakages in the silicon debug stage for production. The consideration of test derivation is both to enhance the yield and to improve the product quality with low-test cost. The electrical modeling of DRAM cell, test selection and guardband determination are introduced. It is shown that the newly created tests can distinguish the normal and abnormal cell current leakages. Promising wafer test results are obtained that the wafer test yield is improved over 8% by laser repairing the weak (defective) cells with the spares and it achieves a reasonable final test quality.

In this paper, a methodology to develop fault models for hierarchical linear systems which are composed of operational amplifiers (OP) is demonstrated and presented. The methodology at first presents a transfer function model for the open-loop OP based on analysis of element faults at the transistor level. Then it derives a transfer function model for the closed loop OP based on the derived open-loop OP level model, again a higher level fault model for a module which is composed of closed loop OPs. The models can handle ac faults. The benchmark state-variable filter is used as an example to demonstrate for this methodology. An application of the derived models to Monte Carlo simulation to save computation time is also demonstrated.

Chips with defects, which escape the test, will cause a quality problem and will hurt goodwill and decline revenue. It is important to look for the defect root causes and to derive the prevention strategy. In this paper a case study of a 64M-DRAM is used to demonstrate the approaches of failure analysis in silicon debug stage and, consequently the determination of the tests for production. The consideration of test derivation is both to enhance the yield and to improve the product quality with low test cost. The root cause, electrical modeling of defects, test selection and guardband determination are introduced. Finally, a quantitative measure is given to show the value of failure analysis for a high volume DRAM product.

This paper presents a novel scheme to diagnose single and double faults for linear analog circuits. The scheme first proposes a simple transformation procedure to transform the tested linear analog circuit into a discrete signal flow graph, then constructs "diagnosing evaluators", which model the faulty components, to form a diagnosis configuration to diagnose the faults through digital simulation. This saves much computation time. Furthermore, a simple method to un-power the OP's is also proposed to differentiate equivalent faults. The scheme can diagnose faults in passive components as well as faults in OP's.

In this work, IDDQ current for deep submicron VLSI in year 2011 is estimated with a statistical approach according to the International Technology Roadmap for Semiconductors 1999 Edition considering process variations and different input vectors. The estimated results show that the standard deviation of the IDDQ current is proportional to the square root of the circuit size and the IDDQ currents of the defect-free and the defective devices, which are of the size up to 1/spl times/10/sup 7/ gates, are still differentiable under the condition of random process deviations and input vectors. Two new IDDQ testing schemes, which detect the defective current based on the two separate IDDQ distributions, are proposed. From the study, it is concluded that IDDQ testing is still applicable for the deep submicron VLSI for the next ten years.

This work proposes an approach to generate weighted random patterns which can maximally excite a circuit during its burn-in testing. The approach is based on a probability model and a maximization procedure to obtain signal transition probability distribution for primary inputs and to generate weighted random patterns according to the obtained probability distribution. It can especially generate weighted random patterns to excite particularly selected "weak nodes" of the circuit in order to expose the early failure of these nodes. Experimental results show that this approach can increase the power dissipation of the total circuit nodes up to 26.68% and the switching activity of particularly selected nodes up to 41.51% respectively.

This paper proposes a method to select flip-flops for partial reset and/or partial scan for sequential circuits to increase their testability. The method gives weights for flip-flops for consideration for partial reset and/or scan based on information on required states for activating faults and the number of faults which propagate to flip-flops, which are obtained during test generation. Since the above information offers the reasons causing the untestable and/or hard-to-detect faults, the method is very efficient in locating flip-flops for partial reset and/or scan to ease test generation task. Experiments showed that this method selected less number of flip-flops for partial reset and scan while produced more testable circuits for benchmark circuits.

This paper investigates detection and location for single faults in odd-even sorting networks. In the work, we have found that three tests are enough to locate single link fault and four tests are sufficient to detect single sorting element fault in an odd-even sorting network. For location tests for sorting element faults, the numbers of tests depend on the type of faults occurring at the sorting element. For most types of sorting element faults, the numbers are less than four specific tests. For the other types of faults, we have presented the test generation procedure and binary search procedures to generate the tests. The numbers of location tests are less than (n+log/sub 2/n), where n=log/sub 2/N and N is the number of inputs of the sorting network.

In this paper, the optimum functional patterns for CMOS operational amplifier are proposed based on an analysis to find the maximum difference between the good circuit and the faulty circuit for a CMOS operational amplifier. The theoretical and simulation results show that the derived test patterns do give the maximum difference at the output even when the circuit has a "soft" fault. The results have also been applied to generate test patterns for a programmable gain/loss mixed signal circuit.

For sequential circuit test pattern generation incorporating backward justification, we need to justify the values on flip-flops to activate and propagate fault effects. This takes much time when the values to be justified on flip-flops appear to be invalid states. Hence, it is desirable to know invalid states, either dynamically during the justification process or statically before proceeding to test generation. This paper proposes algorithms to identify, before test generation, invalid states for sequential circuits without reset states. The first algorithm explores all valid states from an unknown initial state to search the complete set of invalid states. The second algorithm finds the complete set of invalid states from searching the reachable states for each state. The third algorithm searches the invalid states which are required for test generation to help stop justification early by analyzing dependency among flip-flops to simulate each partial circuit. Experimental results on ISCAS benchmark circuits show that the algorithms can identify invalid states in short time. The obtained invalid states were also used in test generation, and it was shown that they improved test generation significantly in test generation time, fault coverage, and detection efficiency, especially for larger circuits and for those that were difficult to generate.

While an integrated circuit is fabricated and tested, errors may be introduced during manufacturing and testing processes. An IC development flow driven by yield improvement, which includes two stages of testing evaluations, called engineering and production runs, for test error classification and cancellation, is proposed in this paper. Six error-syndromes including mask, process, scrape, probe-card, probe-pin, and test-specification errors are classified by wafer map analysis. Test Errors can be canceled by either re-testing or re-adjusting the test-specification derived from designer/application-engineer and test engineer. An ASIC CMOS chip is used to validate the proposed testing process and the yield of this product is improved up to 16% in production line.

For sequential circuit test pattern generation, the information on invalid states will help greatly on backward justification to reduce the test generation time. This paper proposes three algorithms to find invalid states for sequential circuit test generation. The first two algorithms search the complete set of invalid states by exploring all valid states and reachable states respectively. The first algorithm is efficient for circuits having more invalid states than valid states while the second algorithm is efficient for circuits having more valid states than invalid states. The third algorithm searches only the invalid states that are required for test generation to stop justification early. Experimental results on ISCAS benchmark circuits show that the algorithm can identify invalid states in short time and can help improve test generation significantly in the fault coverage, detection efficiency, and generation time.

Conventional fault relationships are mostly restricted to faults at a gate or within a fanout free region. In this paper, we analyze the fault relationships beyond the fanout free region for general digital logic circuits. An improved fault collapsing procedure is proposed and applied to several kinds of combinational benchmark circuits and 31 sequential benchmark circuits to collapsing faults. Improvements of 2-8% for an initial set of target faults of a circuit can be obtained. For some of circuits, the reduction ratio can have up to 20% improvement. This may save a lot of time in test generation and fault simulation processes.

This paper presents a theoretical analysis to identify robust untestable path delay faults. It first classifies the path reconvergence of fanouts into seven cases and deduces the necessary conditions to robustly test path delay faults for each case. It then proposes a procedure, based on the deduced conditions, to identify the robust untestable path delay faults. The procedure was applied to ISCAS 85' circuits and it was found that the robust untestable faults occupy a high percentage of the total path delay faults. In addition, it also presents a method to estimate the number of robust untestable path delay faults for a circuit.

A study is made of single-fault fault collapsing in sequential logic circuits. Two major phenomena, self-hiding (SH) and delayed reconvergence (DR), which arise from the existence of feedback paths and storage elements in sequential circuits, are analyzed and found to cause the dominance relationship which is valid in combinational circuits but no longer valid in sequential circuits. A fault-collapsing procedure is proposed to collapse faults in sequential circuits. It first collapses faults in the non-SAD (self-hiding and delayed-reconvergence) gates of the combinational part of the sequential circuit and then further collapses faults by identifying the prime fan-out branches. Finally, it collapses faults in feedback lines. The collapsed faults constitute a sufficient representative set of prime faults.>

A study of fault collapsing for synchronous sequential circuits is presented. Two phenomena, self-hiding and delay-reconvergence, which invalidate the combinational fault dominance relationship in sequential circuits are identified. These phenomena are caused by the existence of feedback paths and storage elements in sequential circuits. From this analysis, a single-fault fault-collapsing procedure for synchronous irredundant sequential circuits is proposed to reduce the faults for which test has to be generated. This procedure can be applied not only to a nonscan mode circuit, but also to a full-scan and a partial-scan mode circuit by cutting the inputs and outputs of scannable D flip-flops as the primary outputs and inputs of the circuit, respectively. This procedure has been applied to collapse faults for the 31 benchmark sequential circuits, and a 57% reduction in the number of faults as compared with the total number of original faults has been obtained.>