This paper proposes the symbol-level-stochastic Chase decoding algorithm (S-SCA) for the Reed-Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes, which is a soft-input soft-output (SISO) decoder. By the efficient usage of void space between constellation points for q-ary modulations and using soft information at the input of the decoder, the S-SCA is capable of outperforming conventional symbol-levelChase algorithm (S-CA) with a less computational cost. Since the S-SCA starts with the randomized generation of likely testvectors, it reduces the complexity to polynomial order and also it does not need to find the least reliable symbols to generate testvectors. The symbol-level-search bitwise-transmission stochastic Chase algorithm (SSBT-SCA) is also introduced for RS codes over binary phase shift keying (BPSK) transmission that is capable of generating symbol-level test-vectors with reduced complexity and to better mitigate burst errors. Simulation results show that by increasing the number of test-vectors, the performance of the algorithm can asymptotically approach the maximum-likelihood (ML) bound. The S-SCA provides near 2 dB decoding gain in comparison with S-CA for a (31, 25) RS code using 32-QAM, when 1024 test-vectors are used. Furthermore, the algorithm provides near 3 dB additional gain with 1024 test-vectors compared with S-CA that uses 65536 iterations when a (255, 239) RS code is used in an additive white Gaussian noise (AWGN) channel. For the Rayleigh fading channel and the same code, the algorithm provides more than 5 dB gain. Furthermore, for (63, 57) BCH codes and 8-PSK modulation, the proposed algorithm provides 3 dB gain with less complexity.

Lifestyle interventions with the focus on diet are crucial in self-management and prevention of many chronic conditions, such as obesity, cardiovascular disease, diabetes, and cancer. Such interventions require a diet monitoring approach to estimate overall dietary composition and energy intake. Although wearable sensors have been used to estimate eating context (e.g., food type and eating time), accurate monitoring of dietary intake has remained a challenging problem. In particular, because monitoring dietary intake is a self-administered task that involves the end-user to record or report their nutrition intake, current diet monitoring technologies are prone to measurement errors related to challenges of human memory, estimation, and bias. New approaches based on mobile devices have been proposed to facilitate the process of dietary intake recording. These technologies require individuals to use mobile devices such as smartphones to record nutrition intake by either entering text or taking images of the food. Such approaches, however, suffer from errors due to low adherence to technology adoption and time sensitivity to the dietary intake context. In this article, we introduce EZNutriPal , 1 an interactive diet monitoring system that operates on unstructured mobile data such as speech and free-text to facilitate dietary recording, real-time prompting, and personalized nutrition monitoring. EZNutriPal features a natural language processing unit that learns incrementally to add user-specific nutrition data and rules to the system. To prevent missing data that are required for dietary monitoring (e.g., calorie intake estimation), EZNutriPal devises an interactive operating mode that prompts the end-user to complete missing data in real-time. Additionally, we propose a combinatorial optimization approach to identify the most appropriate pairs of food names and food quantities in complex input sentences. We evaluate the performance of EZNutriPal using real data collected from 23 human subjects who participated in two user studies conducted in 13 days each. The results demonstrate that EZNutriPal achieves an accuracy of 89.7% in calorie intake estimation. We also assess the impacts of the incremental training and interactive prompting technologies on the accuracy of nutrient intake estimation and show that incremental training and interactive prompting improve the performance of diet monitoring by 49.6% and 29.1%, respectively, compared to a system without such computing units.

As the complexity of the power grid increases, it becomes more susceptible to failures and cascading outages. Therefore, the resiliency of the power grid is severely jeopardized under fault conditions, unforeseen disturbances, and cyber or physical attacks. A common approach to alleviate vulnerabilities and further improve operational security is to recognize the critical lines or generators and adopt suitable remedial action schemes. In this paper, we use a power flow-based method to assess the vulnerability of the system before and after applying remedial action schemes. We focus on a modified version of the IEEE 9 bus system in Powerworld to examine our method. Our simulation results demonstrate the improvement in the system's resiliency.

In this work, we propose a physical gateway, which resembles a modified dental implant that goes directly through gum or other soft tissues inside the oral cavity, to establish a secure and permanent connection to wired implantable health monitoring and controlling (IHMC) devices and systems. The proposed physical gateway has parts acting as external access points that have terminals for cables, wires, fiber optics, or tubes that go through the gateway to IHMC devices and systems to allow transmission of signals or materials to or from the implanted devices. This novel feature can be utilized for powering IHMC devices and systems with high functionality and computational power. Furthermore, it facilitates securely communicating with IHMC devices and systems with vital duties and allows transferring materials for refilling the tanks inside these devices and systems or transferring some samples and substances from inside body to outside without requiring additional invasive operations.

High-speed and low-area decoders for low-density parity-check (LDPC) codes with very long block lengths are challenging to implement due to the large amount of nodes and edges required. In this paper we implement a decoder for a (32643, 30592) LDPC code that has variable nodes of degree 7, check nodes degrees of 111 and 112, and 228501 edges, making fully-parallel hardware implementation unfeasible. We analyze the structure of this code and describe a method of replacing the complex interconnect with a local, area-efficient version. We develop an modular architecture resulting in a low-complexity partially-parallel decoder architecture based on the offset min-sum algorithm. The proposed decoder is shown to achieve a minimum gain of 92% in area utilization, compared to an extremely optimistic area estimation of the fully-parallel decoder that neglects the interconnection overhead. Synthesis in 65 nm CMOS is performed resulting in a clock frequency of 370 MHz and a throughput of 24 Gbps with an area of 7.99 mm2.

In this paper, we present LDPC decoder designs based on gear-shift algorithms, which can use multiple decoding algorithms or update rules over the course of decoding a single frame. By first attempting to decode using low-complexity algorithms, followed by high-complexity algorithms, we increase energy efficiency without sacrificing error correction performance. We present the GSP and IGSP algorithms, and ASIC designs of these algorithms for the 10 Gbps Ethernet (2048,1723) LDPC code. In 65nm CMOS, our pipelined GSP decoder achieves a core area of 5.29mm2, throughput of 88.1 Gbps, and energy efficiency of 39.3 pJ/bit, while our IGSP decoder achieves a core area of 6.00mm2, throughput of 100.3 Gbps, and energy efficiency of 14.6 pJ/bit. Both algorithms achieve error correction performance equivalent to the offset min-sum algorithm. The throughput per unit area and energy efficiency of these decoders improve upon state-of-the-art decoders with comparable error correction performance.

Low-density parity-check codes are attractive for high throughput applications because of their low decoding complexity per bit, but also because all the codeword bits can be decoded in parallel. However, achieving this in a circuit implementation is complicated by the number of wires required to exchange messages between processing nodes. Decoding algorithms that exchange binary messages are interesting for fully-parallel implementations because they can reduce the number and the length of the wires, and increase logic density. This paper introduces the Relaxed Half-Stochastic (RHS) decoding algorithm, a binary message belief propagation (BP) algorithm that achieves a coding gain comparable to the best known BP algorithms that use real-valued messages. We derive the RHS algorithm by starting from the well-known Sum-Product algorithm, and then derive a low-complexity version suitable for circuit implementation. We present extensive simulation results on two standardized codes having different rates and constructions, including low bit error rate results. These simulations show that RHS can converge faster on average than existing state-of-the-art decoding algorithms, leading to improvements in throughput and energy efficiency.

Despite the outstanding performance of non-binary low-density parity-check (LDPC) codes over many communication channels, they are not in widespread use yet. This is due to the high implementation complexity of their decoding algorithms, even those that compromise performance for the sake of simplicity. In this paper, we present three algorithms based on stochastic computation to reduce the decoding complexity. The first is a purely stochastic algorithm with error-correcting performance matching that of the sum-product algorithm (SPA) for LDPC codes over Galois fields with low order and a small variable node degree. We also present a modified version which reduces the number of decoding iterations required while remaining purely stochastic and having a low per-iteration complexity. The second algorithm, relaxed half-stochastic (RHS) decoding, combines elements of the SPA and the stochastic decoder and uses successive relaxation to match the error-correcting performance of the SPA. Furthermore, it uses fewer iterations than the purely stochastic algorithm and does not have limitations on the field order and variable node degree of the codes it can decode. The third algorithm, NoX, is a fully stochastic specialization of RHS for codes with a variable node degree 2 that offers similar performance, but at a significantly lower computational complexity. We study the performance and complexity of the algorithms; noting that all have lower per-iteration complexity than SPA and that RHS can have comparable average per-codeword computational complexity, and NoX a lower one.

We introduce two dithered belief propagation decoding algorithms to lower the error floor with a minimal hardware overhead. One of the algorithms can additionally improve the decoding performance in the waterfall region using a large iteration limit but with a negligible increase in the average time complexity.

We propose dithered belief propagation decoding algorithms to reduce the number of decoding failures of a belief propagation decoder and lower the error floor. The random nature of the algorithms enables a low hardware complexity compared to previously reported techniques. We introduce two dithering methods that target check node operations and channel input values, respectively. We present simulation results that confirm the error rate gains in the floor region, and that relate those gains with the maximum number of decoding iterations. The results show that the first algorithm can achieve good error rate gains with a low iteration limit. For the second algorithm, results show that with a large iteration limit, high FER gains are possible. Furthermore the average time complexity remains the same as that of a standard belief propagation algorithm.

We study analog decoders in an abstract level and show that their dynamic equations can change with message representation domain. This result, which is in contrast with the behavior of conventional discrete-time iterative decoders, is derived based on continuity requirement for messages that are passed between processing nodes in analog decoders. In this letter, this requirement is met by assigning low-pass filters between processing nodes that remain unchanged for different message representation domains.

In this paper, we show an ideal analog min-sum decoder, in the log-likelihood ratio domain, can be considered as a piecewise linear system. Many theoretical aspects of these decoders, thus, can be studied analytically. It is also shown that the dynamic equations can become singular for codes with cycles. When it is non-singular, the corresponding dynamic equations can be solved analytically to derive outputs of the decoder. We study the relationship between singularity and error floor and prove that absorption sets with degree two check nodes are singular graphs and under specific conditions the dynamic equations of an analog min-sum decoder can be reduced to that of an absorption set. The proposed approach paves the way for further analytical analysis on the dynamics of analog min-sum decoders and error floor in low-density parity-check codes.

This paper presents a Relaxed Half-Stochastic (RHS) low-density parity-check (LDPC) decoding algorithm that uses some elements of the sum-product algorithm (SPA) in its variable nodes, but maintains the low-complexity interleaver and check node structures characteristic of stochastic decoders. The algorithm relies on the principle of successive relaxation to convert binary stochastic streams to a log-likelihood ratio (LLR) representation. Simulations of a (2048, 1723) RS-LDPC code show that the RHS algorithm can outperform 100-iterations floating-point SPA decoding. We describe approaches for low-complexity implementation of the RHS algorithm. Furthermore, we show how the stochastic nature of the belief representation can be exploited to lower the error floor.

In this paper, we propose a binary message-passing algorithm for decoding low-density parity-check (LDPC) codes. The algorithm substantially improves the performance of purely hard-decision iterative algorithms with a small increase in the memory requirements and the computational complexity. We associate a reliability value to each nonzero element of the code's parity-check matrix, and differentially modify this value in each iteration based on the sum of the extrinsic binary messages from the check nodes. For the tested random and finitegeometry LDPC codes, the proposed algorithm can perform as close as about 1 dB and 0.5 dB to belief propagation (BP) at the error rates of interest, respectively. This is while, unlike BP, the algorithm does not require the estimation of channel signal to noise ratio. Low memory and computational requirements and binary message-passing make the proposed algorithm attractive for high-speed low-power applications.

In this paper, we propose a binary message-passing algorithm for decoding low-density parity-check (LDPC) codes. The algorithm substantially improves the performance of purely hard-decision iterative algorithms with a small increase in the memory requirements and the computational complexity. We associate a reliability value to each nonzero element of the code's parity-check matrix, and differentially modify this value in each iteration based on the sum of the extrinsic binary messages from the check nodes. For the tested random and finite-geometry LDPC codes, the proposed algorithm can achieve performance as close as 1.3 dB and 0.7 dB to that of belief propagation (BP) at the error rates of interest, respectively. This is while, unlike BP, the algorithm does not require the estimation of channel signal to noise ratio. Low memory and computational requirements and binary message-passing make the proposed algorithm attractive for high-speed low-power applications.

In this paper, we show that an ideal analog min-sum decoder, in the log-likelihood ratio domain, can be considered as a piecewise linear system. Many theoretical aspects of these decoders, thus, can be studied analytically. It is also shown that the dynamic equations can become singular and degrade the decoding performance. When the decoder is nonsingular, the corresponding dynamic equations can be solved analytically to derive outputs of the decoder. The proposed approach paves the way for further analytical analysis on the dynamics of analog min-sum decoders.

This letter is concerned with the implementation of iterative decoding algorithms in analog integrated circuits. We study the convergence speed and the throughput of analog decoders for low-density parity-check codes, and show that they depend on the code, the decoding algorithm, the signal-to-noise ratio, and the average time constant of the analog circuit interconnections. However, they are not a function of the variance of the time constants. The analysis presented here can be used for selecting suitable codes and decoding algorithms for analog decoding. Furthermore, it can be used to estimate the throughput of an analog decoder, if the average time constant of the analog circuit is known

Conventional iterative decoding with flooding or parallel schedule can be formulated as a fixed-point problem solved iteratively by a successive substitution (SS) method. In this paper, we investigate the dynamics of a continuous-time (asynchronous) analog implementation of iterative decoding, and show that it can be approximated as the application of the well-known successive relaxation (SR) method for solving the fixed-point problem. We observe that SR with the optimal relaxation factor can considerably improve the error-rate performance of iterative decoding for short low-density parity-check (LDPC) codes, compared with SS. Our simulation results for the application of SR to belief propagation (sum-product) and min-sum algorithms demonstrate improvements of up to about 0.7 dB over the standard SS for randomly constructed LDPC codes. The improvement in performance increases with the maximum number of iterations, and by accordingly reducing the relaxation factor. The asymptotic result, corresponding to an infinite maximum number of iterations and infinitesimal relaxation factor, represents the steady-state performance of analog iterative decoding. This means that under ideal circumstances, continuous-time (asynchronous) analog decoders can outperform their discrete-time (synchronous) digital counterparts by a large margin. Our results also indicate that with the assumption of a truncated Gaussian distribution for the random delays among computational modules, the error-rate performance of the analog decoder, particularly in steady state, is rather independent of the variance of the distribution. The proposed simple model for analog decoding, and the associated performance curves, can be used as an "ideal analog decoder" benchmark for performance evaluation of analog decoding circuits.

Current-mode circuits are presented for implementing analog min-sum (MS) iterative decoders. Proposed circuits are devised based on current mirrors. Therefore, in any fabrication technology that accurate current mirrors can be designed, analog MS decoders can be implemented. The functionality of the proposed modules was verified by implementing an analog MS decoder for a (32,8,10) regular LDPC code in 0.18-mum CMOS technology. In low signal to noise ratios when the circuit imperfections are dominated by the noise of the channel, the measured error correcting performance of this chip in steady-state condition surpasses that of the conventional MS decoder, and is close to the performance predicted by the earlier work on the dynamics of the continuous-time analog decoding by Hemati and Banihashemi, ISIT2004. At a throughput of 24 Mb/s, loss in the coding gain compared to the conventional MS decoder at BER of 10-3is about 0.3 dB. To the best of our knowledge, this decoder has the highest throughput and the lowest power/speed ratio among the reported analog CMOS iterative decoders

Conventional iterative decoding with flooding or parallel schedule can be formulated as a fixed-point problem solved iteratively by the successive substitution (SS) method. In this work, we investigate the dynamics of continuous-time asynchronous analog implementation of iterative decoding, and show that it can be approximated as the application of the well-known successive overrelaxation (SOR) method for solving the fixed-point problem. We observe that SOR with the optimal relaxation factor can considerably improve the performance of iterative decoding for short low-density parity-check (LDPC) codes compared to SS. Our simulation results for the application of SOR to belief propagation (sum-product) and min-sum algorithms demonstrate improvements of up to about 0.7 dB over the standard SS for randomly constructed LDPC codes. The improvement in performance increases with the maximum number of iterations and by accordingly reducing the relaxation factor. The asymptotic result, corresponding to infinite maximum number of iterations and infinitesimal relaxation factor represents the performance of analog continuous-time asynchronous iterative decoding. This means that under ideal circumstances continuous-time asynchronous analog decoders can outperform their discrete-time synchronous digital counterparts by a large margin. The proposed model for analog decoding, and the associated performance curves, can be used as an "ideal analog decoder" benchmark for performance evaluation of analog decoding circuits.

Iterative decoding with flooding schedule can be formulated as a fixed-point problem solved iteratively by successive substitution (88) method. In this work, we model continuous-time analog (asynchronous) iterative decoding by a first-order differential equation, and show that it can be approximated as the application of the well-known successive over relaxation (SOR) method for solving the fixed-point problem. Simulation results for belief propagation (sum-product) and min-sum algorithms confirm that SOR, which is in general superior to the simpler 88 method, can considerably improve the performance of iterative decoding for short codes. The improvement in performance increases with the maximum number of iterations and by reducing the step size in SOR, and the asymptotic result, corresponding to infinite maximum number of iterations and infinitesimal step size represents the performance of continuous-time analog iterative decoding. This means that under ideal circumstances continuous-time analog decoders can outperform their discrete-time digital counterparts by a large margin. Moreover, the results obtained by the proposed model are surprisingly close to the results of circuit simulation of a min-sum analog decoder presented in [S. Hemati et al., 2003]. Our work also suggests a general framework for improving iterative decoding algorithms on graphs with cycles, even for synchronous digital implementations.

In this paper, a novel current-mode approach is proposed for implementing basic building blocks of an analog iterative decoder. The decoder is based on the so-called min-sum algorithm (also referred to as max-sum or max-product) and can be used to decode powerful coding schemes such as low-density parity-check (LDPC) codes and turbo codes. The proposed circuits can be implemented by standard CMOS technology, which means lower fabrication cost and/or simpler design compared to previously reported analog iterative decoders that are based on BiCMOS or sub-threshold CMOS technology. To demonstrate the functionality of the proposed design, simulation results based on TSMC 0.18mm CMOS technology for a (7,4) Hamming code are also presented.