SystemC, users and tool providers are at a crossroads. More and more companies are using SystemC; however EDA companies are hesitant to give a full commitment to SystemC tools, especially at system-level. There are several reasons for this dichotomy. While users seem excited about SystemC for its technical qualities for system-level design, tool providers may not share this excitement because of the current small market for such tools. Are the existing (free) reference implementation and the current small market for system level tools to blame, or are there any technical issues impeding the fast development of SystemC tools? Among the SystemC users from industry and academia there is currently some uncertainty about the future availability of state of the art EDA tools supporting SystemC. This panel brings together industrial SystemC users as well as EDA companies to discuss these issues. The industrial panellists will present the current situation regarding the use of SystemC in industry, its importance (or lack thereof) for system design and future needs for such tools. The tool providers will explain their current position regarding the commitment to SystemC and clarify their future plans for supporting it.

To reduce the number of synthesis and layout iterations, we present a new delay optimization technique, which inserts buffers based on back-annotated detailed routing information. During optimization, inserted buffers are assumed to be placed on the appropriate location of original wires so as to calculate accurate wire RC delay. With forward annotated location information of inserted buffers, the layout system attempts to preserve patterns of original wires using the ECO technique. Our experimental results show that this technique combined with the conventional gate sizing technique achieves up to 41.2% delay reduction after the initial layout.

We present a new model for circuits which have memory elements using conditional clocking, This is termed as the “gated” clock problem. Conventionally most of the recent efforts in timing analysis focus on memory elements controlled by clock signals only, We describe a simple restriction on the conditional signale which makes automatic verification easy. An algorithm to solve the timing verification problem for the case of restricted circuits based on previous approaches is given.