SPHINCS+ is the sole hash-based digital signature scheme among the selected post-quantum cryptography (PQC) in 2022. This algorithm possesses the ability to resist attacks from both classical and quantum computers. Due to the extensive computations and different data widths for various parameters, its hardware implementation faces the weakness of long operation time, large area requirement, and low flexibility. This paper presents an efficient and reconfigurable SPHINCS+ processor. The proposed on-the-fly WOTS+ public key generation scheme with unified chain address generator accelerated the most time-consuming operations. This optimization achieves efficient resource utilization. A security switch mechanism resolves the bit misalignment among different data widths with resource reduction. Finally, we introduce a grouped subtree and segmented signature streaming scheme. They reduce the memory to 16k bytes. The processor consumes 29410 LUTs, 14090 FFs, 4 BRAMs on Artix-7 FPGA and achieves$1.04\times/2.41\times $ATPs (area-time-product) optimizations in Sign/Verify with the advantage of supporting all security levels of SPHINCS+.

SPHINCS+ is a selected hash-based post-quantum cryptography (PQC) for digital signature due to its promised security and simple cryptographic operations. However, the excessive storage requirements and potential side channel attack may be the obstacle in its practical application. In this paper, a compact signature streaming scheme is proposed, saving storage consumption by 88%. Besides, two timing attacks: breakpoint and saving signature attack are presented. These crack critical information for grafting tree attack to carry out a universal forgery. A fake signature compensation protection is designed as their countermeasure with 2×128 bits register and free storage. The lightweight, timing attack resistant processor consumes 5832 LUT, 2794 FF, 1 BRAM, representing lowest/second-lowest consumption in LUT(FF)/BRAM among existing designs, and achieves 1.11×/7.25×/20× area time product (ATP) optimizations in LUT/FF/BRAM.