A hierarchical synthesis methodology for analog and mixed-signal systems is presented that fully in a novel way integrates topology selection at all levels. A hierarchical system optimizer takes multiple topologies for all the building blocks at each hierarchical abstraction level, and generates optimal topology combinations using multi-objective evolutionary optimization techniques. With the presented methodology, system-level performance trade-offs can be generated where each design point contains valuable information on how the systems performances are influenced by different combinations of lower-level building block topologies. The generated system designs can contain all kinds of topology combinations as long as critical inter-block constraints are met. Different topologies can be assigned to building blocks with the same functional behavior, leading to more optimal hybrid designs than typically obtained in manual designs. In the experimental results, three different integrator topologies are used to generate an optimal system-level exploration trade-off for a complex high-speed DeltaSigma A/D modulator

This paper describes key points and experimental validation in the development of a bottom--up hierarchical, multi--objective evolutionary design methodology for analog blocks. The methodology is applied to a continuous--time ΔΣ A/D converter for WLAN applications, to generate a set of Pareto--optimal design solutions. The generated performance tradeoff offers the designer access to a set of optimal design solutions, from which the designer can choose a satisfactory design point according to the performance specifications. The presented method takes advantage of the Pareto--optimal performance solutions of the hierarchical lower--level sub--blocks to generate the overall Pareto--optimal set at system level. The way the lower--level performance tradeoffs are combined and propagated to higher hierarchical levels, is one of the major key points in the bottom--up methodology. The experimental results validate the methodology for a 7--block hierarchical decomposition of a complex high--speed ΔΣ A/D modulator for a WLAN 802.11a/b/g standard.

A third-order continuous-time DeltaSigma analog-to-digital converter is designed for the conversion of an input signal bandwidth of 10MHz. Design optimization towards minimal power consumption is demonstrated for the high-speed, low-power building blocks of the modulator. The presented converter achieves a dynamic range of 72dB and a signal-to-noise-and-distortion-ratio of 66dB. The modulator consumes 7.5mW. It is integrated in a 0.18mum standard CMOS technology and occupies an area of 1.65mm2