Researchers, based primarily on theoretical analysis of different coverage metric, have proposed the need to cover small delay defect (SDD). There is very little silicon data justifying the need to add SDD tests to the manufacturing flow. This paper attempts to fill this gap. A high volume manufacturing experiment to ascertain the added screening capability of defective parts and infant mortality of FAST_TDF tests are described. Quantitative silicon data are presented.

Existing commercial power sign-off tools analyze the functional mode of operation for a small time window. The detailed analysis used makes such tools impractical in determining test peak power where a large amount of scan shift cycles have to be analyzed. This paper proposes an approximate test peak power analysis flow capable of computing test peak power at each power bump in the design. The flow uses physical design information, like power grid, power bump location, packaging information, along with the design netlist. We present correlation studies, on industrial design, and show the proposed flow to correlate within 5%of the accurate commercial power sign-off tool. In addition, we demonstrate that this flow, unlike the commercial power sign-off tool, can process a very large number of transition delay tests in a reasonable time.

Clock gating is widely used in modern integrated circuits as a means of reducing dynamic power consumption. In this paper we present a comprehensive analysis of the impact of clock gating during test. We then propose a new type of test point called Clock Gate Test Points. Similar to classic test point techniques, clock gate test points help in increasing the test coverage as well as reducing the number of test patterns and thus test time. We also outline techniques for applying the proposed test points in a design. We present the results of coverage improvement and test pattern reduction with the proposed method for several large industrial circuits. Our results show that with the proposed method, in many cases, more than 2.0% improvement in transition delay fault coverage can be achieved and the number of test patterns can be reduced by more than 50% for the same fault coverage. Furthermore, the proposed test points add very little area overhead and do not impact the circuit performance.

The usefulness of scan tests with multiple fault activation cycles to improve the coverage of transistor stuck-open faults is investigated. A recent work demonstrated that tests with more than one fault activation cycle can detect additional transition delay faults and inline resistance faults when compared to two-pattern tests applied using the broadside or skewed-load methods. We extend this work to show that such tests can also be used for testing additional transistor stuck-open faults. Experimental results for coverage improvement in several ISCAS-89 benchmark circuits will be discussed.

Scan chains contain a high percentage of the transistors in logic parts of VLSI designs. Nevertheless, faults inside scan cells are not directly targeted by scan based tests currently used, and they are assumed to be detected by what are called flush tests. Recently we investigated the detectability of stuck-at, stuck-on and stuck-open faults internal to scan chains using existing tests. We also proposed new flush tests and appropriate ordering of flush tests to achieve higher fault coverage. In this paper, we investigate detection of a set of scan cell internal bridging faults extracted from layout. We show that the detection of some zero-resistance non-feedback bridging faults requires two-pattern tests. Half-speed flush tests we proposed earlier to improve the coverage of stuck-at, stuck-on and stuck-open faults also detect additional bridging faults. We classify the undetectable faults based on the reasons for their undetectability. We observe that the driver strengths of the scan cell inputs can be optimized to improve the bridging fault coverage. Both zero-resistance and nonzero-resistance bridging fault models are considered in this work. A low power supply voltage based test method and IDDQ testing are examined for resistive bridging fault detection.

Small delay defect (SDD) testing is expected to become more prevalent as technology nodes continue to shrink and design frequencies continue to increase. In this paper, we critically examine previously published methods for evaluating SDD coverage and identify their shortcomings as an accurate and practical coverage metric. We propose an accurate method for measuring the coverage of small delay defects by any given pattern set. We demonstrate that the proposed metric overcomes the identified shortcomings of previously published approaches. For several ISCAS and industrial circuits, we generate test patterns and compare their SDD coverage values using different methods. Experimental results also demonstrate that the proposed method is several times faster to compute. Finally, we evaluate different testing strategies for screening small delay defects.

Shrinking feature size and increased wire density increase the likelihood of occurrence of bridge related defects. N- detect based pattern sets are used commonly to improve the detection of bridge defects. However, achieving high bridge coverage requires deterministic bridge sites extraction from physical layout and bridge fault pattern generation. In this paper, we present a comprehensive comparative analysis about the effectiveness of deterministic bridge fault patterns and n-detect patterns for two large designs (90 and 65 nm). We show that extracting different types of bridge faults is required as they represent different unique defect sites. Simulation results show that n-detect patterns have very poor bridge coverage performance and commonly used metric bridge coverage estimate (BCE) does not relate to the true bridge fault coverage. Finally, we discuss the DPPM impact for deterministic bridge fault and n-detect stuck-at patterns for the 90 nm design.

Testing for small delay defects is critical to guarantee that the manufactured silicon is timing-related defect free and to reduce quality loss associated with delay defects. Commercial solutions available for testing of small delay defects result in very high pattern count and run time. In this paper, we present two effective approaches for generating timing-aware transition fault patterns that target small delay defects. We identify a subset of transition faults that should be targeted by the timing-aware ATPG; while for the rest of the faults, classic non-timing-aware transition fault patterns can be generated. Experimental results for several industrial benchmarks show that the proposed approaches result in up to 75% reduction in test pattern count compared to existing timing-aware ATPG approaches.

The objective of using logic BIST for online and periodic testing is to identify defects, like opens, resulting from the wear and tear of the circuit. We have shown that existing test sets have a low coverage for open defects located in scan flip-flops, even though such defects may affect functional operation. Existing Logic BIST structures suffer from the same limitations. A novel Logic BIST architecture to detect such defects is proposed. Unlike other sequences, like checking experiments, the enhancements are simple and independent of the circuit under test.

Nearly half of the transistors in the logic parts of large VLSI designs typically reside inside scan cells. Faults in scan cells may affect functional operation if left undetected. Such undetected faults may also affect the long term reliability of shipped products. Nevertheless, current test generation procedures do not directly target faults internal to the scan cells. Typically it is assumed that scan chain tests, called flush tests, test the scan cells sufficiently. We showed that flush tests applied at slower clock rates, called half-speed flush tests, and tests for scan cell inputs and outputs, detect stuck-at and stuck-on faults internal to scan cells to a similar extent as checking sequence based tests proposed earlier. In this work, we investigate the detection of opens in transistors internal to scan cells. A new flush test and a new method to apply flush tests are proposed to greatly enhance the coverage of opens. We also propose new scan based tests to further increase the coverage of opens. The proposed tests are shown to achieve the maximum possible coverage of opens in transistors internal to scan cells.

Scan chains contain approximately 50% of the logic transistors in large industrial designs. Yet, faults in the scan cells are not directly targeted by scan tests and assumed detected by flush tests. Reported results of targeting the scan cell internal faults using checking sequences show such tests to be about 4.5 times longer than scan stuck-at test sets and require a sequential test generator, even for full scan circuits. We present the first step in developing an alternative test methodology for scan cell internal faults. Fault detection capability of existing tests (flush tests, stuck-at tests and transition delay fault tests) are quantified. Existing tests are shown to have similar coverage as checking sequences. A new flush test, viz. half-speed flush test, is defined. This new test is shown to add 2.3% and 8.8% to the stuck-at and stuck-on fault coverage, respectively.

We present a new test data compression technique that achieves 10times to 40times compression ratios without requiring any information from the ATPG tool about the unspecified bits. The technique is applied to both single-stuck as well as transition fault test sets. The technique allows aggressive parallelization of scan chains leading to similar reduction in test time. It also reduces tester pins requirements by similar ratios. The technique is implemented using a hardware overhead of a few gates per scan chain.

This paper presents segmented addressable scan (SAS), a test architecture that addresses test data volume, test application time, test power consumption, and tester channel requirements using a hardware overhead of a few gates per scan chain. Using SAS, this paper also presents systematic scan reconfiguration, a test data compression algorithm that is applied to achieve 10× to 40× compression ratios without requiring any information from the automatic-test-pattern-generation tool about the unspecified bits. The architecture and the algorithm were applied to both single stuck as well as transition fault test sets.

Detection of transistor stuck-open faults in CMOS circuits requires two-pattern tests. Transition delay fault model is commonly used to model delay causing defects and it also requires two-pattern tests. In this paper we examine the relationship between the two fault models and propose a method for generating test patterns that achieve maximum coverage of both faults. In the proposed method we use an ATPG program for transition delay faults to generate test patterns for both faults. Experimental results are presented to evaluate the effectiveness of our approach

We describe a novel method to partition flip-flops in scan chains into disjoint groups of flip-flops that are to be driven by independent scan enable signals to achieve higher delay fault coverage. The proposed method to partition flip-flops is motivated by our recent work which demonstrated that driving subsets of flip-flops by independent scan enable signals to launch signal transitions will lead to higher delay fault coverage by broadside tests. As in broadside test none of the scan enable signals need to switch at-speed. Experimental results for delay fault coverage improvement on larger ISCAS-89 benchmark and industrial circuits are presented

We propose a novel delay test method for achieving higher delay fault coverage. Multiple scan enable signals are used none of which require the ability to switch at-speed between launch and capture cycles.

Testing of delay faults require two pattern tests. Broadside and skewed-load testing are two approaches to test for delay faults in scan designs. The broadside approach is often preferred over the skewed-load approach in designs that also use the system clock for scan operations, since skewed-load requires a fast (at-speed) scan enable signal while broadside testing does not. In this paper, we propose new scan flip-flops to improve delay fault coverage for circuits with scan using broadside tests. The proposed flip-flops do not require a control signal to switch at-speed. This is a distinct advantage as the design effort required for timing closure of such control signals is significant. We also propose a circuit topology based flip-flop selection procedure that offers a scalable method for increasing the transition fault coverage. Experimental results on industrial circuits are included