The development of ultralow-power analog front ends for edge artificial intelligence (AI) is actively pursued; however, these front ends suffer from low-frequency selection accuracy, leading to increased training loads for the AI components and higher testing costs. In this article, we propose a novel circuit that fundamentally addresses these issues through direct conversion. By re-evaluating the circuit configurations of the multiplier, harmonic removal filter, and full-wave rectifier (FWR) from scratch, we have miniaturized and integrated an ultralow-power converter that transforms frequency components into pulse sequences. The frequency to be analyzed is determined by the local frequency input to the multiplier, which can be digitally controlled with high precision. In our system, the Q value is adaptively adjusted by the local frequency of the direct conversion, allowing the same circuit configuration to be applied to all frequency nodes, eliminating the need for filter design for each node and providing a highly design-friendly and scalable frequency analysis system.The test chip was fabricated with a 0.18-$\mu $m process, operating at a 1.2-V supply, and outputting power pulse streams corresponding to 11 different frequencies ranging from 500 to 5 kHz. The total operating power was$0.9\mu $W, with an achieved equivalent Q factor ranging from 3.6 to 36. In a training experiment using a convolutional neural network (CNN) speech recognition model constructed with a functional model equivalent to this front end, a recognition rate exceeding 80% was achieved, demonstrating the practicality of this front end.

This paper presents a relative slope-boosting technique for a capacitive sensor circuit based on a relaxation oscillator. Our technique improves jitter, i.e. resolution, by changing both the voltage slope on the sensing and the reference sides with respect to the sensor capacitance. The sensor prototype circuit is implemented in a 180-nm standard CMOS process and achieves resolution of 710 aF while consuming 12.7 pJ energy every cycle of 13.78 kHz output frequency. The measured power consumption from a 1.2 V DC supply is 430 nW.

This work presents a current-starved cross-coupled chaotic oscillator achieving multiple decades of oscillation frequency spanning 2 kHz to 15 MHz. The main circuit characteristics are low-power consumption (<100 nW to 25 μW, at 1 V supply voltage), and controllability of the oscillation frequency, enabling future applications such as in distributed environmental sensing. The IC was implemented in 180 nm standard CMOS process, yielding a core area of 0.028 mm2.

This work presents five different 8-bit fixed point low power hardware implementations of cow behavior classifying axis-parallel decision trees (DT) for a range of five feature sets (FS). Each DT is trained and tested with 3-axis accelerometer data labeled beforehand containing four main behaviors, resting, eating, rumination and moving. Investigation shows a 10% F1- score decrement from software (77.4%) to 8-bit fixed point hardware (67.4%) for the conventional feature set, i.e. average mean and variation of the 3D accelerometer vector magnitude (FS4) due to quantization. The horizontal-longitudinal angle of acceleration of the cow (arctan2(y, x)) is proposed as a new FS together with the vertical z-axis (FS1&FS2). The results of an experimental setup, which simulates a stratified 20% split of the entire dataset from PC to FPGA, shows an average accuracy of 86.81% respectively for FS2. This FS's hardware implementation programmed on a Lattice ICE40UP5K FPGA has a power consumption of 216 μW with a latency of 2.58 s at the frequency of 2.9 kHz resulting in an energy of 557 J per classification, which is competitive with state of the art.

We reported a high-frequency piezoelectric resonator (PZR)-based cascaded fractional-N PLL featuring channel adjusting technique with sub-ppb-order frequency resolution, which can overcome the difficulty using the narrow range GHz PZR. This paper details a design of the proposed cascaded PLL. In order to reduce power consumption of 2nd-PLL, a power-efficient latch for pre-scaler is proposed. 3rd-1st cascaded delta-sigma-modulator can reduce the number of gates. The prototype PLL was fabricated in a 65nm CMOS and achieved 8.484GHz to 8.912GHz output, 180 fs rms-jitter, and −244 dB FOM while consuming 12.7mW.

This paper presents design of the low power RF transceiver [1] which is suitable for wireless sensor network. Using 5.8GHz band has potentiality to achieve small size wireless sensor module because of smaller antenna in higher frequency. The proposed transceiver utilizes different modulation schemes for uplink and downlink to optimize power consumption and spectral efficiency. In addition, supply voltage of 0.5V can reduce the power consumption of overall RF transceiver. The prototype transceiver was fabricated in 65nm CMOS process, and the transmitter achieved EVM of 12.6% while consuming 2.86mW, and the receiver realizes sensitivity of -75dBm while consuming 0.83mW.

This paper presents a low-power RF-CMOS-transceiver IC-module with small antennas on a printed circuit board (PCB). Active mixer-first architecture is employed on a receiver for achieving both acceptable sensitivity and lower power. We also show strategies for lowering power consumption of the transmitter and the phase locked loop (PLL): a high-gain inverter-based resonant-driver and a current-reuse voltage controlled oscillator (VCO). Power saving of the RF circuits is achieved with low supply-voltage design under 0.5V by exploiting forward body bias technique. The use of 5.5-GHz band and a J-shaped folded monopole antennas (JFMA) on the PCB enable to reduce the module footprint, and the module size of 0.78 cc is realized. The proposed transceiver circuit is fabricated in 65 nm CMOS process technology and is mounted on the PCB. 5.5-GHz RF-transceiver operation is succeeded with small power consumption of 1.56 mW under 0.5-V power supply. Output signal-power of the transmitter is −23.2 dBm, and receiver sensitivity is −61.2 dBm.

This paper proposes an ultra-low-power 5.5-GHz PLL which employs a divide-by-4 injection-locked frequency divider (ILFD), which is calibrated by digital circuits, and linearity-compensated varactors for low supply-voltage operation. The proposed PLL was fabricated in 65nm CMOS. It shows a 1-MHz-offset phase noise of -106 dBc/Hz and the total power consumption of 950μW at 5.5 GHz.

This paper proposes an ultra low power pH-monitoring IC featuring a wireless FM-transmitter with duty cycling operation and the use of an Ion Sensitive Field Effect Transistor (ISFET) for dentistry application. The IC achieves wireless communication and pH sensing under very low current consumption thanks to duty cycling operation and heavily stacked-transistor design. 0.18 μm CMOS process technology is used to fabricate a prototype chip, and current consumption of 2.0 μA was measured.

Recently, many game programs have been developed aggressively as hardware on field programmable gate arrays (FPGAs) because of the extremely large solution space of such games as the Connect6 game, Blokus Duo game, and others so that the computational capabilities of computers are currently insufficient to search all possible solutions. This report describes an FPGA acceleration experiment for the Blokus Duo game. The FPGA Blokus Duo Solver was implemented on an Arria II GX FPGA (Altera Corp.). Its operation speed is 25 times faster than C++ based software operation of the same algorithm on a Core i7 processor.

This paper demonstrates a low voltage differential signaling (LVDS)-type on-chip transmission line (TL) interconnect to solve delay issues on global interconnects. The proposed on-chip TL interconnect can achieve 10.5 Gbps signaling and has smaller delay, smaller delay variation and better power efficiency than conventional on-chip interconnects at high-frequencies.

This paper presents a novel small-area distributed mixer for ultrawide-band (UWB) receivers. The proposed mixer uses five 4-port inductors instead of fifteen 2-port inductors to shrink area of the circuit. The proposed mixer achieves conversion gain of -10 dB, noise figure of 15 dB, return loss of less than -10 dB from 2.3 to 6.0 GHz, IIP3 of 13.6 dBm, and the circuit area of 0.51 mm2.

This paper proposes a branching method for on-chip transmission line (TL) interconnects, which can reduce delay and power of global interconnects. A 6-mm-long TL interconnect with a branch is fabricated by using a 0.18 mum standard Si CMOS process, and the measurement result performs 4Gbps signal transmission.

On-chip transmission-line interconnect has been proposed to reduce delay time and power consumption. The transmission line is used to replace long RC interconnects. This paper proposes the methodology to replace RC lines with transmission lines, which are estimated with Wire Length Distribution (WLD). Advantages of on-chip transmission line are discussed from the view point of delay time and power consumption.

Multineuronal recordings have enabled us to examine context-dependent changes in the relationship between the activities of multiple cells. The joint peri-stimulus time histogram (JPSTH) is a much-used method for investigating the dynamics of the interdependence of spike events between pairs of cells. Its results are often taken as an estimate of interaction strength between cells, independent of modulations in the cells' firing rates. We evaluate the adequacy of this estimate by examining the mathematical structure of how the JPSTH quantifies an interaction strength after excluding the contribution of firing rates. We introduce a simple probabilistic model of interacting point processes to generate simulated spike data and show that the normalized JPSTH incorrectly infers the temporal structure of variations in the interaction parameter strength. This occurs because, in our model, the correct normalization of firing-rate contributions is different than that used in Aertsen, Gerstein, Habib, and Palm's (1989) effective connectivity model. This demonstrates that firing-rate modulations cannot be corrected for in a model-independent manner, and therefore the effective connectivity does not represent a universal characteristic that is independent of modulation of the firing rates. Aertsen et al.'s (1989) effective connectivity may still be used in the analysis of experimental data, provided we are aware that this is simply one of many ways of describing the structure of interdependence. We also discuss some measure-independent characteristics of the structure of interdependence.