Demo Data from EDBT 2026 / reviewers in the wild / expert
Dominic Rizzo
dblp:09/5053
· DBLP profile ↗
3ranked-venue papers
0as first author
1since 2021 · last 2022
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Security and privacy · 2 · 1 since 2021Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
2 papers |
Hardware security and side channels · 48% Authentication and access control · 26% Cryptographic protocols and secure computation · 26% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 5 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware security and side channels › hardware vulnerability detection
hardware fuzzing |
0.6 | 1 | 2022 | Fuzzing Hardware Like Software · USENIX Security Symposium 2022 |
Electronic design automation › hardware verification and test › random testing
fuzzing |
0.6 | 1 | 2022 | Fuzzing Hardware Like Software · USENIX Security Symposium 2022 |
Electronic design automation
hardware verification and test |
0.6 | 1 | 2022 | Fuzzing Hardware Like Software · USENIX Security Symposium 2022 |
Authentication and access control
multi-factor authentication |
0.4 | 1 | 2019 | True2F: Backdoor-Resistant Authentication Tokens · IEEE Symposium on Security and Privacy 2019 |
Cryptographic protocols and secure computation › secure computation protocols
two-party protocol |
0.4 | 1 | 2019 | True2F: Backdoor-Resistant Authentication Tokens · IEEE Symposium on Security and Privacy 2019 |
Methods — techniques the papers use, named apart from their topics
coverage-guided fuzzing · 1.1two-party key generation · 0.4ECDSA · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | Fuzzing Hardware Like Software
Timothy Trippel, Kang G. Shin, Alex Chernyakhovsky, Garret Kelly, Dominic Rizzo, Matthew Hicks |
USENIX Security Symposium | 5 |
| 2019 | True2F: Backdoor-Resistant Authentication TokensabstractWe present True2F, a system for second-factor authentication that provides the benefits of conventional authentication tokens in the face of phishing and software compromise, while also providing strong protection against token faults and backdoors. To do so, we develop new lightweight two-party protocols for generating cryptographic keys and ECDSA signatures, and we implement new privacy defenses to prevent cross-origin token-fingerprinting attacks. To facilitate real-world deployment, our system is backwards-compatible with today's U2F-enabled web services and runs on commodity hardware tokens after a firmware modification. A True2F-protected authentication takes just 57ms to complete on the token, compared with 23ms for unprotected U2F. Emma Dauterman, Henry Corrigan-Gibbs, David Mazières, Dan Boneh, Dominic Rizzo |
IEEE Symposium on Security and Privacy | 5 |
| 2006 | GraphStep: A System Architecture for Sparse-Graph AlgorithmsabstractMany important applications are organized around long-lived, irregular sparse graphs (e.g., data and knowledge bases, CAD optimization, numerical problems, simulations). The graph structures are large, and the applications need regular access to a large, data-dependent portion of the graph for each operation (e.g., the algorithm may need to walk the graph, visiting all nodes, or propagate changes through many nodes in the graph). On conventional microprocessors, the graph structures exceed on-chip cache capacities, making main-memory bandwidth and latency the key performance limiters. To avoid this "memory wall," we introduce a concurrent system architecture for sparse graph algorithms that places graph nodes in small distributed memories paired with specialized graph processing nodes interconnected by a lightweight network. This gives us a scalable way to map these applications so that they can exploit the high-bandwidth and low-latency capabilities of embedded memories (e.g., FPGA Block RAMs). On typical spreadingactivation queries on the ConceptNet Knowledge Base, a sample application, this translates into an order of magnitude speedup per FPGA compared to a state-of-the-art Pentium processor. Michael DeLorimier, Nachiket Kapre, Nikil Mehta, Dominic Rizzo, Ian Eslick, Raphael Rubin, Tomás E. Uribe, Thomas F. Knight Jr., André DeHon |
FCCM | 4 |