To realize an energy-efficient transmitter (TX) for ultra-low-power (ULP) Internet-of-Things (IoT) applications, function-reuse oscillator–power-amplifiers (Osc-PAs) provide high efficiency and tight system integration by merging an oscillator ("Osc", either a digitally controlled, DCO, or voltage-controlled, VCO) with a power amplifier (PA) into a single block. This work presents the latest advancements in Osc-PAs for IoT applications. It covers the architectural evolution, design considerations, and limitations of Osc-PAs. Finally, the prospects of reusing and implementing TX Osc-PA to achieve RX-clock generation by leveraging mode-switching techniques in fully integrated transceivers (TRXs) will be discussed.

Despite the potentially superior phase-noise (PN) performance compared to the parallel-tank resonance oscillator, the series-resonance oscillator (SRO) usually suffers from a narrow tuning range (TR) ofmcells as required for oscillation. Typically, enhancing the TR of SRO requires lowering the tank Q-factor at the cost of PN and figure-of-merit (FoM). This paper proposes a quadrature SRO with an enhanced TR using higher-order tanks with a boosted coupling factor by means of trifilar transformers. This maintains the low PN while improving its tuning range (TR) to 22% (i.e., 10.3 to 12.9GHz). Designed in TSMC 28-nm HPC+ CMOS, as per post-layout full-chip simulations, the proposed SRO achieves PN of -124dBc/Hz and -146dBc/Hz at 1 and 10MHz offset, respectively, from the 12.24GHz carrier frequency, while consuming 55mW. This results in an FoM of 188.3–190.1dBc/Hz and an FoMTof 194.7–197.7dBc/Hz across the TR.

In this paper, we present a fully integrated ring-oscillator (RO)-based temperature sensor for quantum computing applications. As the quantum states exhibit an exponential sensitivity to the on-die cryogenic temperature change, any such temperature variation due to, for example, local heating islands arising from the poor thermal conductivity of silicon should be monitored. For this purpose, we exploit a compact RO sensor placed in the vicinity of qubits. The proposed approach employs four differently sized oscillators and two VBGs to generate, in total, eight different temperature-dependent oscillating frequency signals. Then, by performing their polynomial fitting, a linear temperature-frequency compensating model for the proposed sensor is derived. Fabricated in 22 nm FD-SOI technology, the proposed sensor occupies 0.0016 mm2, consumes 128 μW and achieves maximum inaccuracy of ± 2.1 K in a wide temperature range from 3 to 270 K.

In this paper, we present an inverter-based ring oscillator (RO) operating at cryogenic temperatures for quantum computing applications. It employs a low-dropout regulator (LDO) to provide supply voltage for a programmable switched-capacitor system which isolates the supply line of the integrated RO circuit from any noise or perturbations of the external power supply. In anticipation of embedding the RO into a phase-locked loop (PLL), we study the variation of flicker phase noise from cryo to room temperature by indirectly measuring the phase noise (PN) in the 30dB/dec region. The proposed system occupies 0.012mm2and shows 3.5dB integrated PN improvement thanks to the proposed voltage supply noise reduction technique at room temperature (RT) and the FOM is estimated as 121.7dB at cryogenic temperature (CT).

Gain-cell (GC) based eDRAM has been a promising memory topology due to the lower area footprint and energy consumption than its SRAM counterpart. However, the eDRAM suffers from a short retention time in finer technology nodes. Enhancing the retention time requires both pMOS and nMOS devices, but this inadvertently increases the cell size due to the minimum spacing between them. Further, the retention time is dominated by either logic ‘1’ or ‘0’, lowering the overall retention time. In our work, we propose an nMOS-only GC-based 4T GC-eDRAM memory topology that occupies an area comparable to the 3T GC-eDRAM and enhances the retention time by balancing logic ‘0’ and ‘1’ via controlling the leakage path. Designed in GlobalFoundries 22-nm FD-SOI, the post-layout simulation of a dual port 128×128 (4kb) eDRAM memory array shows 610 μW and 490 μW of write and read power consumption at 250 MHz, respectively, while maintaining the retention time of 25 μs. The 4T bit-cell with the logic design rule only occupies 0.12 μm2, which is 1.5× lower than the two-port 8T SRAM cells in the PDK, while 1.1× larger than the single-port 6T SRAM.

This paper presents a machine-learning (ML)-assisted co-design framework for the optimization of open-loop analog linearization in VCO-based ADCs. A deep neural network (DNN) surrogate model is trained on a dataset generated by transistor-level transient simulations of the VCO’s voltage-to-frequency (V -to-f) characteristic. The vast multi-dimensional optimization landscape provided by the VCO’s embedded linearization tuning ‘knobs’ make exhaustive search infeasible. The DNN model enables a rapid exploration of this tuning-knobs landscape to minimize the harmonic-distortion (HD) through an evolutionary genetic algorithm (GA). The ‘predicted’ optimal tuning-knob values are transferred back into the local Cadence simulation environment for further fine-grained gradient-descent adaptation via an integrated Verilog-A self-calibration engine. Applied to the coupled-oscillator-ensemble (COE) circuit architecture, the tuning-knob configurations inferred by the DNN-GA yield simulated third-order HD of 42–52dB for the VCO-based ADC, with a boost to >60dB (i.e., 10-bit performance) using a few iterations of local gradient-descent optimization.

In this paper, we present the characterisation of ring oscillator (RO) test circuits fabricated in GlobalFoundries’ (GF) 22nm fully depleted silicon-on-insulator (FD-SOI) process and operating from 200 K down to 4 K. We investigate ROs using NAND, NOR, and inverter standard cell libraries, including low, regular, and high threshold-voltage versions. Alongside temperature variations, we also consider a change in the power supply of ±5% from a nominal 0.8 V. The ROs demonstrate the combined effect of increased mobility, increased threshold voltage, and leakage current processes at cryogenic temperatures on their operation. By averaging over 81 fabricated ROs using three different delay gates and 2 different flavours, we report a statistical characterisation of their properties in the FD-SOI technology over temperature and supply voltage.

The grand challenge of scaling up quantum computers requires a full-stack architectural standpoint. In this position paper, we will present the vision of a new generation of scalable quantum computing architectures featuring distributed quantum cores (Qcores) interconnected via quantum-coherent qubit state transfer links and orchestrated via an integrated wireless interconnect.

This paper proposes the use of a tunable$LC$resonator to read an array of qubits in a multiplexed fashion, by making the dispersive shift of the targeted qubit dominant. Cavity and circuit electrodynamics (QED) theory is shown to support this idea. The tunable capacitor array, in parallel with a superconducting inductance, is designed to maximize the quality factor by frequency range product,$Q\cdot\Delta\omega$. This approach only requires one RF signal to measure multiple qubits, which can facilitate quantum computing scaling.

A frequency-to-digital converter (FDC) performs the role of precise frequency digitization within a voltage-controlled oscillator (VCO)-based ADC. To be compatible with energy-harvesting (EH) Internet-of-Things (IoT) devices, the development of ultra-low-voltage (ULV) FDCs is crucial, where the primary focus must be directed towards the maximization of data throughput under dramatic constraints of reliability and timing variability associated with deep-subthreshold operation. This article investigates the speed maximization of a 0.2V full-custom ULV FDC design, consisting of an array of several parallel XOR-based FDC units, and the multi-rate decimation-filtering digital back-end. At the core of this broad exploration is a high-speed sense-amplify phase sampler (PS) featuring hardware redundancy, capable of sampling the phase of low-voltage-swing inputs. Particular focus is placed on the yield-based reliability-driven design methodology for the sense-amplify phase-sampling circuits running up to 40MS/s and practical variability-mitigation strategies. To overcome the speed bottleneck in the digital back-end, a fully parallel bitstream-processing architectural composition of the computations for summation and decimation are proposed. Experimental verification through measurements of the FDC integrated within a 10-bit 160kHz bandwidth (BW) open-loop VCO-based ADC across clock frequency with supply variations demonstrate robust operation of the first 0.2V multi-phase FDC in the advanced 28nm CMOS process.

In this paper, a wideband low-noise amplifier (LNA) with a two-fold noise cancellation scheme is proposed. Finetuned for advanced CMOS, the proposed LNA architecture uses a common-gate input branch to provide wideband input matching. It is followed by two stages of the common-source structure which cancels the noise and distortion of the first and second stages and relaxes the design restriction on the first noise-cancellation stage. The provided circuit-level analysis is verified by simulations. The proposed LNA is fabricated in 28-nm CMOS. It achieves a minimum noise figure (NF) of 2.5dB and input return loss (S11) < −15dB over 0.02–2GHz bandwidth while consuming only 4.1mW from a 1V supply and driving an external 50-$\Omega $load. The −3dB power gain (S21) is 18.5dB and IIP3 is +4.25dBm.

This article presents a wide-band suppression technique of flicker phase noise (PN) by means of a gate–drain phase shift in a transformer-based complementary oscillator. We identify that after naturally canceling its second-harmonic voltage by the complementary operation itself, third-harmonic current entering the capacitive path is now the main cause of asymmetry in the rising and falling edges, leading to the$1/f$noise upconversion. A complete$1/f^{3}$PN analysis for the transformer-based complementary oscillator is discussed. By tuning gate–drain capacitance ratio, a specific phase-shiftrangeis introduced at the gate and drain nodes of the cross-coupled pair to mitigate the detrimental effects of ill-behaved third-harmonic voltage, thus lowering the flicker PN. To further reduce the area and improve the PN in the thermal region, we introduce a new triple-8-shaped transformer. Fabricated in 22-nm FDSOI, the prototype occupies a compact area of 0.01mm2and achieves$1/f^{3}$PN corner of 70kHz, PN of −110dBc/Hz at 1MHz offset, figure-of-merit (FoM) of −182dB at 9GHz, and 39% tuning range (TR). It results in the best FoM with normalized TR and area (FoMTA) of −214dB at 1MHz offset.

This paper presents an ultra-lower-power (ULP) digital-to-time-converter (DTC)-assisted fractional-N all-digital phase-locked loop (ADPLL) suitable for IoT applications. A proposed hybrid time-to-digital converter (TDC) extends the vernier-TDC input range with little power overhead in order to overcome the stability issue in the conventional architectures. The hybrid TDC also facilitates a background gain calibration to achieve a stable in-band phase noise insensitive to process, voltage, and temperature (PVT) variations. The implementation of a buffer-cascaded DTC simplifies the design complexity of the fractional-N operation. The ADPLL also features a 200$\mu \text{W}$low-phase-noise inverse-class-F (class-F−1) digitally controlled oscillator (DCO) without the need of two-dimensional (2-D) capacitor tuning for frequency alignment of the fundamental and 2nd-harmonic. Fabricated in 65-nm CMOS, the ULP ADPLL prototype achieves 868fsrmsjitter in a fractional-N channel when consuming only 529$\mu \text{W}$, corresponding to a figure-of-merit (FoM) of −244dB.

Nonlinearity of a digital-to-time converter (DTC) is pivotal to spur performance in DTC-based all-digital phase-locked-loops (ADPLL). In this paper, we characterize and analyze the mismatch of cascaded-delay-unit DTCs. Through an improved built-in-self-test (BIST) time-to-digital converter (TDC) assisted with phase-to-frequency detector (PFD), a measurement system of sub-half-ps accuracy is constructed to conduct the characterization. Fabricated in 28-nm CMOS, the DTC transfer functions are measured, and mismatches are compared against Monte-Carlo simulation results. The integral nonlinearity (INL) results are compared against each other and converted to the in-band fractional spur level when the DTC would be deployed in the ADPLL. The BIST-TDC system thus characterizes the on-chip delays without expensive equipment or complex setup. The effectiveness of adding a PFD into the$\Delta \!\Sigma $loop is validated. The entire BIST system consumes 0.6mW with a system self-calibration algorithm to tackle the analog blocks’ nonlinearities.

This paper presents a simple yet effective$G_{m}$-boosting technique for improving gain and noise performance of millimeter-wave (mm-wave) low-noise amplifiers (LNAs) comprising triple-well transistors typically found in the modern bulk CMOS processes. The proposed technique uses a resistor that connects the p-well and deep n-well terminals of the triple-well transistor, leaving the terminals floating instead of conventionally connecting them to the ground and supply voltage. This arrangement exploits a leakage current through a diode formed between the drain/source and p-well of each transistor, thus autonomously setting its bulk potential for increased transconductance, while ensuring its robustness to the process variation. The improved isolation between the p-well and the substrate further improves the gain and noise performance. We provide a theoretical analysis of this floating resistor-based body biasing method and support it with simulation results. For experimental validation, a two-stage cascode LNA was designed and fabricated in 28-nm bulk CMOS. The measurement results show that 3.3–4dB noise figure (NF) and 19.1–16.1dB gain are achieved at 24.7–29.5GHz. To ensure a fair comparison, another identical LNA with the normally expected triple-well biasing was also fabricated. The proposed method reveals a 0.6dB improvement in minimum NF and an additional ~3.5dB gain without any significant linearity degradation.

In this article, we propose a broadband fully integrated power amplifier (PA) using a waveform shaping harmonic matching network. A comprehensive theory is developed for the proposed multi-resonance harmonic matching network to derive design criteria for achieving wide bandwidth, low insertion loss, and optimum load impedances in the second- and third-harmonic frequency bands. Furthermore, it is shown that this network can be realized using a lower total inductance compared to a standard bandpass network which is an important feature in reducing chip area and fabrication cost. A fully integrated PA prototype is implemented using a 250-nm GaN-on-SiC process with 28-V supply. The PA provides 33.9–36.1dBm output power (at 2–3dB gain compression), 42–51% drain efficiency (DE), 38–48% power-added efficiency (PAE), and 10–12.2dB power gain, across 4.0–6.0GHz. The output-power 1-dB bandwidth is 3.6–5.6GHz (44.5%). For a 64-QAM signal with 8dB peak-to-average power ratio (PAPR) at 5.0GHz, the PA can provide 30.2dBm average output power and 32% average PAE with RMS error vector magnitude (EVM) of −34.0/−32.4/−28.4dB (2.0/2.4/3.8%) for 50/100/200MHz modulation bandwidth, without using digital predistortion (DPD). The maximum average output power and average PAE, under the linearity constraint EVM <−28dB, are respectively 32.1/32.0/30.2dBm and 39/38/32%, for modulation bandwidth of 50/100/200 MHz.

We present an architecture of a Bluetooth low energy (BLE)-compliant receiver which, for the first time ever, breaks the 1mW barrier of power consumption. It is based on a type-II phase-tracking loop and addresses the mutual magnetic coupling between on-chip inductors of a digitally controller oscillator (DCO) and low-noise transconductance amplifier (LNTA), which causes RX performance degradation in the prior-art implementations. An inverter-based inductor-free LNTA is employed instead. The resulting adjacent channel rejection (ACR) improves by 1.5/2.5dB at 2/3MHz offset. By further leveraging current-reuse and switched-capacitor circuitry, this RX achieves the best-in-class FoM of 183.2dB with sensitivity of -93.2dBm. Thanks to the single-channel topology, the proposed RX occupies tiny area of 0.48mm2in 28-nm CMOS.

In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture based on a single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra-low area in 10-nm FinFET CMOS. Underpinned by excellent switches in the FinFET technology, a high turn-on/off capacitance ratio of LC-tank switched capacitors, in addition to an adjustable magnetic coupling technique, yields almost an octave TR from 10.8 to 19.3GHz. A new method to compensate for the tracking-bank resolution can maintain its quantization noise level over this wide TR. A new scheme is adopted to overcome the metastability resolution problem in a fractional-N ADPLL operation. A low-complexity TDC gain estimator reduces the digital core area by progressive averaging and time-division multiplexing. Among the published fractional-N PLLs with an area smaller than 0.1mm2, this work achieves an rms jitter of 725fs in an internal fractional-N mode of ADPLL's phase detector (2.7-4.825GHz) yielding the best overall jitter figure-of-merit (FOM) of -232dB. This topology features small area (0.034mm2), wide TR (56.5%) and good supply noise rejection (1.8%/V), resulting in FOMs with normalized TR (FOMT) of -247dB, and normalized TR and area (FOMTA) of -262dB.

This paper demonstrates a wideband 2.4 GHz$2\times 9$-bit Cartesian radio-frequency digital-to-analog converter (RFDAC). Active-under-coil integration is introduced in the physical implementation, where all key active circuitry is located underneath the matching-network transformer, achieving a core area of merely 0.35 mm2. An$8\times $analog linear interpolation at the RF rate is proposed to suppress replicas close to the carrier while avoiding any high-order and high-speed digital filters in digital processing back-end. The multi-port transformer is adopted in the matching network to improve the back-off efficiency. The measured peak output power and drain efficiency at the center frequency of 2.4 GHz are 17.47 dBm and 17.6% respectively, while the peak efficiency is 19.03%. Moreover, the 6-dB back-off efficiency is at 66% of that at the peak output power. The active-under-coil integration helps this RFDAC to achieve the smallest area among comparable prior arts.

In this paper we demonstrate electrostatic control and feasibility of entanglement in CMOS qubits. We present both single particle and multi-particle methodologies to describe quantum transport using a time-dependent Hamiltonian assuming one spatial degree of freedom. The developed models predict maximally entangled states of electrons controlled electrostatically by external driving fields and interacting via the Coulomb force.

We describe a quantum computing hardware paradigm that exploits the current scaling achievements of mainstream CMOS technology. Just like in a small IC chip, where a single nanometer-sized CMOS transistor can be reliably replicated millions of times to build a digital processor, we propose a new structure of a qubit realized as a CMOS-compatible charge-based quantum dot that can be reliably replicated thousands (or perhaps even millions) of times to construct a quantum processor. Combined with an on-chip CMOS controller, it will realize a useful quantum computer (QC) that can operate at 4 K, which is much higher than the temperature of today's QCs of 15 mK.

The zero/low intermediate frequency (IF) receiver (RX) architecture has enabled full CMOS integration. As the technology scales and wireless standards become ever more challenging, the issues related to time-varying dc offsets, the second-order nonlinearity, and flicker noise become more critical. In this paper, we propose a new architecture of a superheterodyne RX that attempts to avoid such issues. By exploiting discrete-time (DT) operation and using only switches, capacitors, and inverter-based gm-stages as building blocks, the architecture becomes amenable to further scaling. Full integration is achieved by employing a cascade of four complex-valued passive switched-cap-based bandpass filters sampled at 4× of the local oscillator rate that perform IF image rejection. Channel selection is achieved through an equivalent of the seventh-order filtering. A new twofold noise-canceling low-noise transconductance amplifier is proposed. Frequency domain analysis of the RX is presented by the proposed DT model. The RX is wideband and covers 0.4-2.9 GHz with a noise figure of 2.9-4 dB. It is implemented in 65-nm CMOS and consumes 48-79 mW.

In modern RF system on chips (SoCs), the digital content consumes up to 85% of the IC chip area. The recent push to integrate multiple RF-SoC cores is met with heavy resistance by the remaining RF/analog circuitry, which creates numerous strong aggressors and weak victims leading to RF performance degradation. A key such mechanism is injection pulling through parasitic coupling between various LC-tank oscillators as well as between them and strong transmitter (TX) outputs. Any static or dynamic frequency proximity between aggressors (i.e., oscillators and TX outputs) and victims (i.e., oscillators) that share the same die causes injection pulling, which produces unwanted spurs and/or modulation distortion. In this paper, we propose and demonstrate a new frequency planning technique of a multicore TX where each LC -tank oscillator is separated from other aggressors beyond its pulling range. This is done by breaking the integer harmonic frequency relationship of victims/aggressors within and between the RF transmission channels using digital fractional divider based on a phase rotation. Each oscillator's center frequency can be fractionally separated by ~28% but, at the same time, both producing closely spaced frequencies at the phase rotator outputs. The injection-pulling spurs are so far away that they are insignificantly small (-80 dBc) and coincide with the second harmonic of the carrier. This method is experimentally verified in a two-channel system in 65-nm digital CMOS, each channel comprising a high-swing class-C oscillator, frequency divider, and phase rotator.

In this paper, fractional spur suppression techniques for all-digital PLLs (ADPLLs) are summarized. The attention is paid to the recently proposed digital-to-time converter (DTC)-based ADPLL architecture. DTC's nonlinearity dominates the fractional spurs contribution. Its influence is modeled with a pseudo phase-domain ADPLL and its relationship with the spur level is quantitatively described. An LMS algorithm is adopted to calibrate the DTC gain. Furthermore, an improved adaptive algorithm is proposed to suppress the fractional spurs.

In this paper, a digital-to-time converter (DTC) assisting a time-to-digital converter (TDC) as a fractional phase error detector in an ultra-low power ADPLL is proposed and demonstrated in 40nm CMOS. A phase prediction algorithm via the assistance of the DTC reduces the required TDC range, thus saving substantial power. Additionally, a fully digital calibration algorithm is presented and proved to validate the whole ADPLL system and improve the DTC linearity. At 1 V supply voltage, the measured time resolution of the DTC is 22 ps. The TDC resolution is also indirectly measured with a closed-loop 2.4 GHz ADPLL, where -95.3 dBc/Hz in-band phase noise corresponds to a worst-case TDC resolution of 22 ps.

A novel built-in calibration mechanism for a nonlinear digitally-controlled power amplifier (DPA), or its combination with an external power amplifier (PA), is proposed. It allows construction of a digital predistortion mechanism, which is configured based on data collected entirely through processing of internal digital signals in an all-digital PLL (ADPLL)-based transmitter. The proposed technique is suitable not only for characterizing the amplitude and phase transfer function non- linearities and configuring the internal predistortion accordingly, but may also be useful for built-in self-test (BIST) purposes. The proposed technique has been implemented and successfully validated in a commercial single-chip GSM/EDGE radio.

The past several years have successfully brought all-digital techniques to the RF frequency synthesis, which is used for frequency translation between the baseband and RF frequencies in wireless transmitters and receivers. Reference [1] has described the recent journey of digitizing RF frequency synthesizers, such that now they are amenable to nanoscale CMOS technology with area, power and performance metrics well exceeding those of the traditional charge-pump PLL's. This paper examines an important aspect of the all-digital frequency synthesizers, which takes on some of the transmitter functionality by allowing to directly perform the carrier frequency modulation. This is useful in today's wireless system, which either completely rely on the frequency modulation to convey the information or use it as part of a polar vector modulation. A novel multi-rate polar transmitter is proposed in which the modulating data rate is independent from the reference frequency.

The past several years have successfully brought all-digital techniques to the RF frequency synthesis, which could arguably be considered one of the last strong bastions of the traditionally-analog design approaches. With their high sensitivity and high dynamic range requirements, the RF circuits have long had a good excuse to avoid any possible source of digital switching activity. With the constant scaling of CMOS feature size and the merciless push for integration, the existence of almost free and powerful digital logic could not go unnoticed. Hence, the environment was ripe to transform the RF functions into digital realizations, as well as to apply digital assistance to help with the performance of RF circuits. This paper revisits the digitization journey of the traditional charge-pump PLL and offers a few novel techniques to further improve area, current consumption, testability and reliability of frequency synthesizers.

A number of communication applications are moving to digitally motivated architectures for their radio frequency module. This includes GSM-EDGE, WLAN, Bluetooth, GSM-GPRS, WiMAX. The All Digital PLL(ADPLL) forms the core of this architecture. The objective of the ADPLL is to generate a clean carrier frequency fc, based on a input reference frequency fref. As part of the phase error measurement of the PLL, a Time to Digital converter(TDC) is used to measure the delay between frefclock edge and carrier clocking edge. An inverter chain is used to measure this delay as a integer number of basic inverter delay. This measurement error is termed TDC quantization error and effects the phase noise present in the final carrier. Due to the coarse delay of the basic inverter available, TDC introduces large quantization noise at the output of the PLL. This is too high for systems operating at high carrier frequencies or systems which have a tight phase noise requirement. This paper presents techniques to improve TDC quantization noise.

Digital RF Processor (DRPTM)-based GSM/EDGE transmitter is built using dense and fast digital logic and comprises two converters that transform transmit modulation from digital to RF frequency/phase and amplitude analog domains. Using the concept of digital at the service of analog, DRP transmitters employ a number of estimation and compensation algorithms to provide robust performance in the presence of CMOS device variability. This paper describes digital techniques to counter the random and systematic mismatches in the amplitude path of the small-signal DRP transmitter. Furthermore, the DRP-based small signal polar EDGE transmitter utilizes a nonlinear digitally-controlled pre-power amplifier (DPA) with optimized power-added efficiency (PAE). The DPA is used for on-chip combination of the amplitude and phase modulation paths, which exhibit variable transfer characteristics due to process, voltage, temperature and aging. For stringent transmitter (TX) performance requirements, the DPA needs to be linearized in the dynamic TX operational environment. The techniques presented are employed in a commercial Texas Instruments single-chip GSM/EDGE radio realized in nanoscale CMOS.

Radio transmitters using the polar scheme utilize a CO-ORDInate Calculator (CORDIC) to transform the often interpolated baseband data in Cartesian format to its polar equivalent. This non-linear transmission typically results in an increased bandwidth for amplitude and phase modulated signals. In case of digital implementation, each of these amplitude and phase/frequency modulation paths are realized using segmented modulators, with fine resolution achieved by techniques such as sigma-delta modulation. This paper first describes the structure of a digital polar transmitter. This is followed by a study on the impact of the increased bandwidth in the polar domain on the timing alignment accuracy requirements between the amplitude and phase modulation paths. Furthermore, for each high-resolution modulation path the timing accuracy between the integer and the sigma-delta fractional path split is also analyzed.

The paper proposed estimation techniques and compensation algorithms against CMOS device variability in an all-digital RF polar transmitter. The transmitter is built using dense and fast digital logic and comprises two converters that transform transmit modulation from digital to RF frequency/phase and amplitude analog domains. The converters built with segmented banks consist of a large number of unit-weighted devices which exhibit a certain level of random and systematic mismatch. The techniques presented are employed in a commercial single-chip GSM/EDGE radio realized in 90 nm CMOS

This paper describes the mechanism of retimed reference frequency clock (CKR)-induced spurs at the ADPLL radio frequency (RF) output. These spurs appear not only at the average CKR or reference frequency (FREF) and its harmonics, called the reference spurs, but also at the inter-modulation locations related to the amount of inherent jitter in the retimed clock, termed as side spurs. The amplitude of these side spurs, which appear centered on the FREF frequency and its harmonics can be greatly reduced by decreasing the amount of inherited jitter in the generated CKR clock. This paper explains the relationship between the various retiming choices and the location of these side-spurs. Further, specific to a GSM transmitter realized in 90 nm CMOS; a performance analysis of using the channel dependent variable clock frequency (CKV) for retiming without any frequency division is presented.

A new all-digital phase-locked loop (ADPLL) for wireless applications has recently been proposed and commercially demonstrated. It replaces conventional phase/frequency detector and charge pump with a time-to-digital converter (TDC). Analog frequency tuning of a VCO is replaced with an all- digital tuning of a digitally-controlled oscillator (DCO). Due to its digital intensive structure, the ADPLL is well suited for single-chip radio solutions fabricated using state-of-the- art low cost and power nanometer-scale CMOS processes. Being integrated with a digital signal processor (DSP), the ADPLL parameters can be properly controlled and seamlessly reconfigured using the available on-chip DSP unit making the ADPLL a software defined radio (SDR) platform. In this paper, we present a DSP based technique for the fully dynamic control of the ADPLL settling performance that allows the loop band width to be seamlessly widened or narrowed allowing for fast frequency acquisition or tracking with excellent phase noise and spurious performance, respectively. The arbitrary and dynamic control of the frequency synthesizer loop bandwidth will address the dynamically varying nature of a multi-radio multi- standard SDR environment.

RF circuits for multi-GHz frequencies have recently migrated to low-cost digital deep-submicron CMOS processes. Unfortunately, this process environment, which is optimized only for digital logic and SRAM memory, is extremely unfriendly for conventional analog and HF designs. We present fundamental techniques recently developed that transform the RF and analog circuit design complexity to digital domain for a wireless RF transceiver, so that it enjoys the benefits of digital approach, such as process node scaling and design automation. All-digital phase locked loop, all-digital control of phase and amplitude of a polar transmitter, and direct HF sampling techniques allow great flexibility in reconfigurable radio design. Digital signal processing concepts are used to help relieve analog design complexity, allowing one to reduce cost and power consumption in a reconfigurable design environment. Software layers are defined to enable these architectures to develop an efficient software defined radio. VHDL hardware description language is universally used throughout this SoC. The ideas presented have been used in Texas Instruments to develop two generations of commercial digital RF processors: a single-chip Bluetooth radio and a single-chip GSM radio.

We present a system-on-chip (SoC) that integrates a TMS320C54x digital signal processor (DSP), which is commonly used in cellular phones, with a multigigahertz digital RF transmitter that meets the Bluetooth specifications. The RF transmitter is tightly coupled with the DSP and is directly mapped to its address space. The transmitter architecture is based on an all-digital phase-locked loop (ADPLL), which is built from the ground up using digital techniques and digital creation flow that exploit high speed and high density of a deep-submicrometer CMOS process while avoiding its weaker handling of voltage. The frequency synthesizer features a wideband frequency modulation capability. As part of the digital flow, the digitally controlled oscillator (DCO) and a class-E power-amplifier are created as ASIC cells with digital I/Os. All digital blocks, including the 2.4-GHz logic, are synthesized from VHDL and auto routed. The use of VHDL allows for a tight and seamless integration of RF with the DSP. To take advantage of the direct DSP-RF coupling and to demonstrate a software-defined radio (SDR) capability, a DSP program is written to perform modulation of the GSM standard. The chip is fabricated in a baseline 130-nm CMOS process with no analog extensions and features high logic gate density of 150 kgates per mm/sup 2/. The RF transmitter area occupies only 0.54 mm/sup 2/, and the current consumption (including the companion DSP) is 49 mA at 1.5-V supply and 4 mW of RF output. This proves attractiveness and competitiveness of the "digital RF" approach, whose goal is to replace RF functions with high-speed digital logic gates.

This paper presents recent trends in the area of integrated CMOS transceiver design for short distance wireless applications. This application is characterized by very low-cost and low-power so-lutions. Current challenges and recent trends are described and digital-oriented design opportunities for increasing integration out-lined. Signal processing approaches applied to the front-end elec-tronics find an increasing emphasis and are extremely viable. 1.

In this paper, we describe area and power reduction techniques for a low-latency adaptive finite-impulse response filter for magnetic recording read channel applications. Various techniques are used to reduce area and power dissipation while speed and latency remain as the main performance criteria for the target application. The proposed parallel transposed direct form architecture operates on real-time input data samples and employs a fast, low-area multiplier based on selection of radix-8 premultiplied coefficients in conjunction with one-hot encoded bus leading to a very compact layout and reduced power dissipation. Area, speed, and power comparisons with other low-power implementation options are also shown. The proposed filter has been fabricated using a 0.18-/spl mu/m L-effective CMOS technology and operates at 550 MSamples/s. Trading off filter latency to improve speed is also discussed.

In this paper, we describe area and power reduction techniques for a low-latency adaptive finite-impulse response filter for magnetic recording read channel applications. Various techniques are used to reduce area and power dissipation while speed remains as the main performance criterion for the target application. A parallel transposed direct form architecture operates on real-time input data samples and employs a fast, low-area multiplier based on selection of radix-8 pre-multiplied coefficients in conjunction with one-hot encoded bus leading to a very compact layout and reduced power dissipation. Area, speed and power comparisons with other low-power implementation options are also shown. The proposed filter has been fabricated using a 0.18 µm L-effective CMOS technology and operates at 550 MSamples/s.