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Shuo-Hsien Hsiao

dblp:09/5880 · DBLP profile ↗
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3ranked-venue papers
2as first author
0since 2021 · last 1995
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 2 · 1 first-authorSystems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Interconnection networks and networks-on-chip · 68% Performance modeling and evaluation · 32%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip › switching network
multistage interconnection network
0.031995
A new model for the performance evaluation of synchronous circuit switched multistage interconnection networks · IEEE/ACM Trans. Netw. 1995
Performance analysis of single-buffered multistage interconnection networks · IEEE Trans. Commun. 1994
Performance Evaluation of Circuit Switched Multistage Interconnection Networks Using a Hold Strategy · IEEE Trans. Parallel Distributed Syst. 1992
Performance modeling and evaluation
queueing models
0.021995
A new model for the performance evaluation of synchronous circuit switched multistage interconnection networks · IEEE/ACM Trans. Netw. 1995
Performance Evaluation of Circuit Switched Multistage Interconnection Networks Using a Hold Strategy · IEEE Trans. Parallel Distributed Syst. 1992
Interconnection networks and networks-on-chip › packet switching
buffered switching
0.011994
Performance analysis of single-buffered multistage interconnection networks · IEEE Trans. Commun. 1994
Interconnection networks and networks-on-chip › switching
circuit switching
0.011992
Performance Evaluation of Circuit Switched Multistage Interconnection Networks Using a Hold Strategy · IEEE Trans. Parallel Distributed Syst. 1992
Performance modeling and evaluation › queueing models
closed queueing networks
0.011992
Performance Evaluation of Circuit Switched Multistage Interconnection Networks Using a Hold Strategy · IEEE Trans. Parallel Distributed Syst. 1992
Interconnection networks and networks-on-chip
interconnection networks
0.011992
Performance Evaluation of Circuit Switched Multistage Interconnection Networks Using a Hold Strategy · IEEE Trans. Parallel Distributed Syst. 1992
Interconnection networks and networks-on-chip › multiprocessor interconnection
processor-memory interconnection
0.011992
Performance Evaluation of Circuit Switched Multistage Interconnection Networks Using a Hold Strategy · IEEE Trans. Parallel Distributed Syst. 1992

Methods — techniques the papers use, named apart from their topics

queueing model · 0.0probabilistic analysis · 0.0simulation · 0.0analytical modeling · 0.0queueing network model · 0.0closed-form analysis · 0.0
YearPublicationVenuePosition
1995 A new model for the performance evaluation of synchronous circuit switched multistage interconnection networks
abstract
Patel (1981) proposed a probabilistic approach to analyze the performance of synchronous multistage interconnection networks (MINs) based on a uniform reference model and the assumption of independent requests. Patel's model and analytical results have been widely adopted by numerous researchers as a basis to investigate various aspects of MINs. We study in detail the effects of the independence assumption on the accuracy of system performance and point out the factors which cause an inaccuracy. A new queueing model is then proposed and is shown to be very accurate. Since only six states are needed, independent of the size of MINs, this new model is very efficient computationally.
C. Y. Roger Chen, Shuo-Hsien Hsiao, Abdulaziz S. Almazyad
IEEE/ACM Trans. Netw.2
1994 Performance analysis of single-buffered multistage interconnection networks
abstract
A new model for the performance evaluation of single-buffered multistage interconnection networks (MINs) is proposed. Previous models proposed in solving this problem are either not accurate enough or only applicable to a special case where the switching elements (SEs) are 2/spl times/2 crossbars. This new model allows the analysis of a MIN with SEs of arbitrary sizes (i.e., a/spl times/a) and, through extensive simulations, has been shown to be very accurate. Since only three states are required at each stage of a MIN, this model is efficient computationally.>
Shuo-Hsien Hsiao, C. Y. Roger Chen
IEEE Trans. Commun.1
1992 Performance Evaluation of Circuit Switched Multistage Interconnection Networks Using a Hold Strategy
abstract
The performance evaluation of processor-memory communications for multiprocessor systems using circuit switched interconnection networks with a hold strategy is performed. Message size and processor processing time are considered and shown to have a significant effect on the overall system performance. A closed queuing network model is proposed such that only (n+2) states are required by the proposed model, in contrast to (n/sup 2/+3n+4)/2 states needed in previous studies, where n is the number of stages of the multistage interconnection network. Since a closed-form solution is obtained, the behavior of a complete cycle of memory access through multistage interconnection networks can be accurately analyzed and various performance bounds can be obtained.>
Shuo-Hsien Hsiao, C. Y. Roger Chen
IEEE Trans. Parallel Distributed Syst.1