The floating point performance of superscalar SPARC processors is evaluated based on empirical data horn 12 benchmarks.This evaluation is done in the context of two software instruction scheduling optimization, loop unrolling and software pipelining, and for three machine models we term, 1-scalar, 2-scalar and 4-scalar.We also consider the effect of the memory system on the performance improvements.Superscalar hardware alone exhibit little performance improvement without software optimization.Of the two scheduling methods we study, software pipelining more effectively takes advantage of increased hardware parallelism, and achieves near optimal speedup on the 4-scalar machine model.The performance of loop unrolling is restricted by the limited number of floating point registers in the SPARC architecture.The best performance level is obtained by applying both optimization techniques.A superscalar SPARC processor can provide improved tloating point performance but with significant software and hardware development costs.

In this paper, cache design is explored for large high-performance multiprocessors with hundreds or thousands of processors and memory modules interconnected by a pipe-lined multi-stage network. The majority of the multiprocessor cache studies in the literature exclusively focus on the issue of cache coherence enforcement. However, there are other characteristics unique to such multiprocessors which create an environment for cache performance that is very different from that of many uniprocessors.