Today's mobile communications systems are usually interference limited in terms of their overall capacity. In the paper we present a novel powerful yet simple interference cancellation algorithm for receive diversity systems. The algorithm for Rake receivers is based on the correlation between the identical multi-path delays occurring on the antennas. The attractive simplicity is due to the separate handling of different Rake fingers yielding a low complexity with the lack of large matrices. Nevertheless, the new algorithm exhibits an excellence performance, which is proven by simulation results.

In this paper, we analyze the evolution of output decisions of adaptive firms in an environment of oligopolistic competition. The firm might either choose to produce one of several existing product variants or try to establish a new product variant on the market. The demand for each individual product variant is subject to a life cycle, but aggregate demand for product variants is constant over time. Every period each firm has to decide whether to produce the product again, introduce a new product variant itself (which generates an initial advantage on that market), or follow another firm and change to the production of an already established product. Different firms have heterogeneous abilities to develop products and imitate existing designs; therefore, the effects of the decision whether to imitate existing designs or to innovate differ between firms. We examine the evolution of behavior in this market using an agent-based simulation model. The firms are endowed with simple rules to estimate market potentials and market founding potentials of all firms, including themselves, and make their decisions using a stochastic learning rule. Furthermore, the characteristics of the firms change dynamically due to "learning by doing" effects. The main questions discussed are how the success and the optimal strategy of a firm depend on the interplay between characteristics of the industry and properties of the firm.

Due to the rapid increase in the system complexity of modern telecommunication products, two main challenges exist for a system design flow meeting the arising demands: 1) provide a platform for fast algorithmic and architectural design exploration and optimization from system to gate level, which guarantees high quality of results (QoR) and enables full and seamless design verification; 2) provide a platform for design reuse. In this paper, we show how a design flow based on fast system simulation, behavioral synthesis and power analysis is used for the commercial implementation of an ADPCM (Adaptive Differential Pulse Code Modulation) codec module in record time, simultaneously meeting all design constraints and creating a versatile system and HDL model ready for design reuse.

While the mobile communication electronics industry's appetite grows for ever more functions and ever higher levels of integration, the complexity of these large designs is creating a discontinuity in the method by which these systems are designed. We take a close look at what is causing the design discontinuity, and how new design technologies are used to design advanced digital communications systems for portable and wireless communication applications. We examine how system-level design tools closely tied to silicon design implementation and verification technologies are enabling the creation of digital communications ICs in record time. We take several examples of commercially available silicon solutions designed using these methodologies-a G.721 ADPCM speech codec for cordless telephony and a complete variable-rate digital-video broadcast receiver for the DVB-S broadcast standard.

Just as advanced digital communications techniques have been employed to increase the capacity of cellular systems, similar concepts are being used to extend the capacity and introduce multispeed and multiformat capabilities for portable messaging systems in the paging, and narrowband PCS arena. In this paper, we review the problem of designing digital receivers for these markets, where product life cycles are dramatically shortening. We first take a brief look at the standards uses in paging and narrowband PCS. Then, we examine the structure of digital receivers, focusing on the structure of baseband digital modems. We then propose and demonstrate a design methodology for the VLSI implementation of key algorithm modules using dataflow modeling and behavioral synthesis. Finally, we conclude with some observations on design technologies for PCS chipsets.

The CORDIC algorithm is a well-known iterative method for the efficient computation of vector rotations, and trigonometric and hyperbolic functions. Basically, CORDIC performs a vector rotation which is not a perfect rotation, since the vector is also scaled by a constant factor. This scaling has to be compensated for following the CORDIC iteration. Since CORDIC implementations using conventional number systems are relatively slow, current research has focused on solutions employing redundant number systems which make a much faster implementation possible. The problem with these methods is that either the scale factor becomes variable, making additional operations necessary to compensate for the scaling, or additional iterations are necessary compared to the original algorithm. In contrast we developed transformations of the usual CORDIC algorithm which result in a constant scale factor redundant implementation without additional operations. The resulting "Differential CORDIC Algorithm" (DCORDIC) makes use of on-line (most significant digit first redundant) computation. We derive parallel architectures for the radix-2 redundant number systems and present some implementation results based on logic synthesis of VHDL descriptions produced by a DCORDIC VHDL generator. We finally prove that, due to the lack of additional operations, DCORDIC compares favorably with the previously known redundant methods in terms of latency and computational complexity.

At present, the Viterbi algorithm (VA) is widely used in communication systems for decoding and equalization. The achievable speed of conventional Viterbi decoders (VD's) is limited by the inherent nonlinear add-compare-select (ACS) recursion. The aim of this paper is to describe system design and VLSI implementation of a complex system of fabricated ASIC's for high speed Viterbi decoding using the "minimized method" (MM) parallelized VA. We particularly emphasize the interaction between system design, architecture and VLSI implementation as well as system partitioning issues and the resulting requirements for the system design flow. Our design objectives were 1) to achieve the same decoding performance as a conventional VD using the parallelized algorithm, 2) to achieve a speed of more than 1 Gb/s, and 3) to realize a system for this task using a single cascadable ASIC. With a minimum system configuration of four identical ASIC's produced by using 1.0 /spl mu/ CMOS technology, the design objective of a decoding speed of 1.2 Gb/s is achieved. This means, compared to previous implementations of Viterbi decoders, the speed is increased by an order of magnitude.

Soft output decoding algorithms have been attracting considerable attention for concatenated or iterative decoding systems. The most prominent is the soft output Viterbi algorithm (SOVA), which can be regarded as an approximation to the optimum symbol by symbol detector, the symbol by symbol MAP algorithm. The MAP algorithm is a block detector, i.e. it requires completed reception of a terminated block of received symbols, which prevents an efficient real-time implementation. Therefore, up to now, the SOVA was considered to be the more attractive alternative. In this paper, we first introduce an algebraic formulation for the MAP. Using this formulation, a novel real-time MAP algorithm (SMAP) is derived, and it is proved that in terms of hard decoding performance, the SMAP is equivalent to the VA with path memory truncation and best state decoding. The finally presented SMAP architectures provide a competitive alternative to the known SOVA architectures for soft output decoding applications.

The CORDIC algorithm is well known as an efficient method for the computation of trigonometric/hyperbolic functions and vector rotations. The achievable throughput and the latency of CORDIC processors using conventional arithmetic are determined by the carry propagation occurring in additions/subtractions, since the CORDIC iterations are directed by the signs of intermediate results. Using a redundant number system, much higher throughput is possible due to the elimination of carry propagation, but an exact sign detection can not be implemented efficiently. The authors derive transformations of the original CORDIC algorithm which result in partially fixed iteration sequences no longer dependent on intermediate signs for the CORDIC vectoring mode as well as the rotation mode. Very fast and efficient carry-save architectures using redundant absolute value computation resulting from the transformed algorithms are described. A CORDIC processor (rotation mode) is presented as an implementation example which to the best of the authors knowledge is the fastest CMOS CORDIC realization today.>

We present a three-stage method for segmenting NMR-datasets of the head into 3D-regions corresponding to different brain matter classes, liquid containing structures, cranium, and background. Our technique works from the beginning with 3D-regions, whose internal ’grey’ values as well as shapes are described by stochastic models. The first phase starts by assuming the entire dataset as consisting of only one region, and then recursively extracts those areas which are not compatible with this hypothesis. During this step, special emphasis is given to the problem of accurately locating the region surfaces. In the second stage, a Bayes classifier groups the regions into different categories, like brain matter, liquid, cranium, and background. Classification errors are corrected largely automatically during the third stage by applying simple knowledge about the topological relationships between the classes.