M. G. Parker

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3ranked-venue papers

3as first author

0since 2021 · last 1997

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-authorGraphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems 1 paper		Integrated circuit design · 100%
Theoretical computer science 1 paper		Coding theory · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

Topic	Papers	Last	Evidence papers
Integrated circuit design › digital circuit design arithmetic circuit design	1	1997	Modular Arithmetic Using Low Order Redundant Bases · IEEE Trans. Computers 1997
Integrated circuit design › digital circuit design › arithmetic circuit design modular arithmetic	1	1997	Modular Arithmetic Using Low Order Redundant Bases · IEEE Trans. Computers 1997
Coding theory › finite fields › finite field arithmetic number theoretic transform	1	1997	Modular Arithmetic Using Low Order Redundant Bases · IEEE Trans. Computers 1997

Methods — techniques the papers use, named apart from their topics

redundant number systems · 0.0redundant number system · 0.0

Year	Publication	Venue	Position
1997	Modular Arithmetic Using Low Order Redundant Bases abstract N-digit, radix-α bases are proposed for VLSI implementation of redundant arithmetic, mod m, wherem= ±1,m≠±1, for 0 < j < N and m is prime. These bases simplify arithmetic overflow and are well suited to redundant arithmetic. The representations provide competitive, multiplierless T-point number theoretic transforms, mod m, where Tl N or Tl 2N. M. G. Parker, Mohammed Benaissa	IEEE Trans. Computers	1
1994	Fault-Tolerant Linear Convolution using Residue Number Systems abstract This paper proposes a fault-tolerant linear convolution architecture using Residue Number Systems (RNS) and Polynomial Residue Number Systems (PRNS). The RNS and PRNS are both given error-detection capability by the addition of redundant residue channels, and the combined redundancy enables error-correction without explicit error-decoding. The method is simple, fast, and amenable to VLSI implementation.> M. G. Parker, Mohammed Benaissa	ISCAS	1
1993	Bit-serial, VLSI architecture for the implementation of maximum-length number-theoretic transforms using mixed basis representation M. G. Parker, Mohammed Benaissa	ICASSP (1)	1