Demo Data from EDBT 2026 / reviewers in the wild / expert
Nimish Shrivastava
dblp:09/6770
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1995
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware reliability and fault tolerance · 70% Embedded and real-time systems · 30% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware reliability and fault tolerance › fault-tolerant architecture
fault-tolerant processor arrays |
0.0 | 1 | 1995 | Optimal Reconfiguration Algorithms for Real-Time Fault-Tolerant Processor Arrays · IEEE Trans. Parallel Distributed Syst. 1995 |
Embedded and real-time systems
real-time scheduling |
0.0 | 1 | 1995 | Optimal Reconfiguration Algorithms for Real-Time Fault-Tolerant Processor Arrays · IEEE Trans. Parallel Distributed Syst. 1995 |
Hardware reliability and fault tolerance
reconfiguration |
0.0 | 1 | 1995 | Optimal Reconfiguration Algorithms for Real-Time Fault-Tolerant Processor Arrays · IEEE Trans. Parallel Distributed Syst. 1995 |
Hardware reliability and fault tolerance
error recovery |
0.0 | 1 | 1995 | Optimal Reconfiguration Algorithms for Real-Time Fault-Tolerant Processor Arrays · IEEE Trans. Parallel Distributed Syst. 1995 |
Methods — techniques the papers use, named apart from their topics
global reconfiguration · 0.0distributed local reconfiguration · 0.0approximation algorithm · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1995 | Optimal Reconfiguration Algorithms for Real-Time Fault-Tolerant Processor ArraysabstractIn this paper we consider the problem of reconfiguring processor arrays subject to computational loads that alternate between two modes. A strict mode is characterized by a heavy computational load and severe constraints on response time while a relaxed mode is characterized by a relatively light computational load and relaxed constraints on response time. In the strict mode, reconfiguration is performed by a distributed local algorithm in order to achieve fast recovery from faults. In the relaxed mode, a global reconfiguration algorithm is used to restore the system to a state that maximizes the probability that future faults occurring in subsequent strict modes will be repairable. Several new results are given for this problem. Efficient reconfiguration algorithms are described for a number of general classes of architectures. These general algorithms obviate the need for architecture-specific algorithms for architectures in these classes. We show that it is unlikely that similar algorithms can be obtained for related classes of architectures since the reconfiguration problem for these classes is NP-complete. Finally, a general approximation algorithm is described that can be used for any architecture. Experimental results are given, suggesting that our algorithms are very effective.> Ran Libeskind-Hadas, Nimish Shrivastava, Rami G. Melhem, C. L. Liu 0001 |
IEEE Trans. Parallel Distributed Syst. | 2 |