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Haiyu Huang 0001

dblp:09/7450-1 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 2018
0000-0002-5596-4590ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Computer networks · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 61% Interconnection networks and networks-on-chip · 30% Energy-efficient computing · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip
optical interconnection networks
0.112009
O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration · DAC 2009
Electronic design automation › physical design › routing
optical routing
0.112009
O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration · DAC 2009
Electronic design automation
physical design
0.112009
O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration · DAC 2009
Energy-efficient computing › low-power design
low-power interconnect
0.012009
O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration · DAC 2009

Methods — techniques the papers use, named apart from their topics

minimum spanning tree · 0.1integer linear programming · 0.1
YearPublicationVenuePosition
2018 Advanced Wireless Communications and Mobile Computing Technologies for the Internet of Things
Haiyu Huang 0001, Kejie Lu, Giovanni Pau 0002, Pai-Yen Chen
Wirel. Commun. Mob. Comput.1
2009 O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration
abstract
In this work, we present a new optical routing framework, O-Router for future low-power on-chip optical interconnect integration utilizing silicon compatible nano-photonic devices. We formulate the optical layer routing problem as the minimization of total on-chip optical modulator cost (laser power consumption) with Integer Linear Programming technique under various detection constraints. Key techniques for variable number reduction and routing speedup are also explored and utilized. O-Router is tested on optical netlist benchmarks modified from top global nets of ISPD98/08 routing benchmarks. O-Router experimental results are compared with conventional minimum spanning tree algorithm, demonstrating an average of over 50% improvement in terms of total on-chip optical layer power reduction.
Duo Ding, Haiyu Huang 0001, Ray T. Chen, David Z. Pan
DAC3