Demo Data from EDBT 2026 / reviewers in the wild / expert
Subhasis Das
dblp:09/9299
· DBLP profile ↗
2ranked-venue papers
2as first author
0since 2021 · last 2016
0000-0001-5557-3058ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Memory systems · 74% Energy-efficient computing · 26% |
Topics — the 7 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
cache |
0.2 | 1 | 2016 | Reuse Distance-Based Probabilistic Cache Replacement · ACM Trans. Archit. Code Optim. 2016 |
Memory systems › cache management
cache replacement |
0.2 | 1 | 2016 | Reuse Distance-Based Probabilistic Cache Replacement · ACM Trans. Archit. Code Optim. 2016 |
Memory systems › memory hierarchy › cache hierarchy
last-level cache |
0.2 | 1 | 2016 | Reuse Distance-Based Probabilistic Cache Replacement · ACM Trans. Archit. Code Optim. 2016 |
Energy-efficient computing › power management › memory power management
cache energy reduction |
0.2 | 1 | 2015 | SLIP: reducing wire energy in the memory hierarchy · ISCA 2015 |
Memory systems › cache management
cache insertion policy |
0.2 | 1 | 2015 | SLIP: reducing wire energy in the memory hierarchy · ISCA 2015 |
Memory systems
cache management |
0.2 | 1 | 2015 | SLIP: reducing wire energy in the memory hierarchy · ISCA 2015 |
Memory systems › memory hierarchy
cache hierarchy |
0.1 | 1 | 2015 | SLIP: reducing wire energy in the memory hierarchy · ISCA 2015 |
Methods — techniques the papers use, named apart from their topics
sampling · 0.2reuse distance · 0.2probabilistic replacement · 0.2reuse distance prediction · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2016 | Reuse Distance-Based Probabilistic Cache ReplacementabstractThis article proposes Probabilistic Replacement Policy (PRP), a novel replacement policy that evicts the line with minimum estimated hit probability under optimal replacement instead of the line with maximum expected reuse distance. The latter is optimal under the independent reference model of programs, which does not hold for last-level caches (LLC). PRP requires 7% and 2% metadata overheads in the cache and DRAM respectively. Using a sampling scheme makes DRAM overhead negligible, with minimal performance impact. Including detailed overhead modeling and equal cache areas, PRP outperforms SHiP, a state-of-the-art LLC replacement algorithm, by 4% for memory-intensive SPEC-CPU2006 benchmarks. Subhasis Das, Tor M. Aamodt, William J. Dally |
ACM Trans. Archit. Code Optim. | 1 |
| 2015 | SLIP: reducing wire energy in the memory hierarchyabstractWire energy has become the major contributor to energy in large lower level caches. While wire energy is related to wire latency its costs are exposed differently in the memory hierarchy. We propose Sub-Level Insertion Policy (SLIP), a cache management policy which improves cache energy consumption by increasing the number of accesses from energy efficient locations while simultaneously decreasing intra-level data movement. In SLIP, each cache level is partitioned into several cache sublevels of differing sizes. Then, the recent reuse distance distribution of a line is used to choose an energy-optimized insertion and movement policy for the line. The policy choice is made by a hardware unit that predicts the number of accesses and inter-level movements. Subhasis Das, Tor M. Aamodt, William J. Dally |
ISCA | 1 |