Spoofing attacks present a significant challenge to automotive and indoor radars by generating false stationary or moving targets. These attacks, capable of injecting spurious human signatures, can trigger false emergency braking in automotive radars and disrupt indoor radars by simulating abnormal vital signs. Despite the demonstrated success of Doppler spoofing techniques using phase shifters and time-modulated metasurfaces, effective mitigation strategies remain unexplored in the literature. This paper introduces a novel Dual Slope FSK-FMCW waveform to concurrently mitigate both Range and Doppler spoofing attacks across various devices, particularly within indoor localization and vital sign monitoring applications. We provide a rigorous mathematical analysis validating the waveform’s efficacy against Doppler spoofing, supported by comprehensive simulation results.

Gait alterations associated with health conditions such as Parkinson’s and Alzheimer’s underscore the critical need for early detection to enhance treatment and care outcomes. Presently, gait monitoring poses challenges due to its expense and complexity. Biomedical radars emerge as potential solutions, enabling vital sign estimation and gait pattern classification. Additionally, an in-depth analysis of the swinging motion of the upper limbs can further refine gait detection, offering improved in-home care for the elderly. This study explores the feasibility of utilizing a 2 GHz Frequency-Modulated Continuous Wave (FMCW) radar for gait analysis, with a specific focus on upper limb swing parameters. Our research showcases the efficacy of FMCW radar in an indoor setting to extract arm swing parameters, presenting a pathway for cost-effective and efficient gait monitoring. These findings carry substantial promise for augmenting in-home care and support, particularly for elderly individuals.

Spoofing attacks pose a significant threat to automotive and biomedical radars. While the conventional BlueFMCW radar waveforms can mitigate close-in spoofing attacks from Digital Radio Frequency Memory (DRFM) and synchronization-based spoofing attacks, they fail to mitigate the Frequency Domain Spoofing (FDS) attacks, which are low-cost and require no synchronization with the victim radar. To address this limitation, we propose a Dual-Slope BlueFMCW radar waveform that enables the mitigation of distance spoofing attacks from both close-in DRFM devices and FDS devices. A new signal processing flow is developed to reject spoofed targets introduced by FDS devices while spreading close-in spoofed targets from DRFM-based spoofing device across multiple range bins. Extensive mathematical derivation and simulation results validate the effectiveness of the proposed Dual-slope BlueFMCW radar waveform in countering both types of spoofing attacks simultaneously.

This study presents a compact, on-chip analog probe module (APM) to augment the IEEE 1149.4 (or P1687.2) standard for efficiently probing multiple internal nodes. The complete approach to APM implementation, from conceptualization to practical application, is discussed in detail. The APM aims to utilize a minimum area for a maximum number of probe channels, achieving an optimal size of 4:15. At the transistor level, the design minimizes the impact of glitches in asynchronous operations through a symmetrical layout and a unique arrangement of all probe channels. However, glitches in asynchronous circuits can still exist; hence, a state transition matrix (STM) concept is devised. STMs help visualize hazardous transitions, allowing the identification of a common hazard-free transition sequence suitable for hardware implementation. The verified APM design is integrated with several analog/RF circuits fabricated in a commercially available 0.18-$\mu $m RF-CMOS process as part of a radar-on-chip system. An important APM application of enabling the prediction of an IC’s corner disposition by measuring dc-node voltages during postsilicon IC testing is demonstrated for 16 fabricated ICs.

Universal self-supervised (SSL) algorithms hold enormous promise for making machine learning accessible to high-impact domains such as protein biology, manufacturing, and genomics. We present DABS 2.0: a set of improved datasets and algorithms for advancing research on universal SSL. We extend the recently-introduced DABS benchmark with the addition of five real-world science and engineering domains: protein biology, bacterial genomics, multispectral satellite imagery, semiconductor wafers, and particle physics, bringing the total number of domains in the benchmark to twelve. We also propose a new universal SSL algorithm, Capri, and a generalized version of masked autoencoding, and apply both on all twelve domains---the most wide-ranging exploration of SSL yet. We find that multiple algorithms show gains across domains, outperforming previous baselines. In addition, we demonstrate the usefulness of DABS for scientific study of SSL by investigating the optimal corruption rate for each algorithm, showing that the best setting varies based on the domain. Code will be released at http://github.com/alextamkin/dabs}{http://github.com/alextamkin/dabs

Although state-of-the-art smart speakers can hear a user's speech, unlike a human assistant these devices cannot figure out users' verbal references based on their head location and orientation. Soundr presents a novel interaction technique that leverages the built-in microphone array found in most smart speakers to infer the user's spatial location and head orientation using only their voice. With that extra information, Soundr can figure out users references to objects, people, and locations based on the speakers' gaze, and also provide relative directions. To provide training data for our neural network, we collected 751 minutes of data (50x that of the best prior work) from human speakers leveraging a virtual reality headset to accurately provide head tracking ground truth. Our results achieve an average positional error of 0.31m and an orientation angle accuracy of 34.3° for each voice command. A user study to evaluate user preferences for controlling IoT appliances by talking at them found this new approach to be fast and easy to use.

We propose a digitally intensive, reconfigurable RF transmitter with an integrated, tunable Class-E power amplifier (PA) which can be configured to operate from 0.75 to 2.5 GHz in discrete bands, while delivering an output power of 11.5 dBm up to 1.5 GHz and 6.5 dBm up to 2.5 GHz. Digital signal processing is exploited to suppress sampling spurs up to the harmonics of the carrier, thus eliminating the need for sharp RF filters. The proposed techniques make the transmitter adaptable to signals of different bandwidths and to different carrier frequencies with minimal overhead in power and area when compared to other digital transmitter designs. Digital predistortion is used to linearize the PA. The transmitter also includes clock correction circuitry for correcting duty cycle and quadrature errors. A generic design methodology is mathematically developed for a reconfigurable Class-E PA with a fixed series inductor. This transmitter scales well with technology and can be potentially used for spectrum sharing (SS) applications in fifth generation (5G) radios. Implemented in a 130-nm CMOS technology, the proposed transmitter occupies an area of 1 mm2. A maximum output power of 13.7 dBm with a maximum efficiency of 27% is obtained at 1 GHz.

This paper presents a wideband frequency-translational resistive-feedback receiver (RX), operational from 0.1 to 2.2 GHz. Different blocker suppression techniques are proposed to improve both out-of-band (OOB) compression and weakly nonlinear distortion of the RX. The blockers are first rejected at the RX input using an N-path filter. Then, a blocker current cancellation (BCC) technique is used to mitigate the effect of nonlinearity in the transimpedance amplifier. By introducing an auxiliary path in the RX, the OOB linearity of the RX is further improved by means of frequency-translational noise cancellation (FTNC) and split-BCC. The RX prototype fabricated in a 130-nm CMOS process achieves 2.6-3.2-dB noise figure (NF) and tolerates a 0-dBm blocker at a 50-MHz offset with an NF of 4.9 dB. At 40-MHz offset from the local oscillator (LO), the RX exhibits higher +23-dBm out-of-band input-referred inter modulation product of order 3 (OB-IIP3) without FTNC and higher +26 dBm OB-IIP3 with FTNC.

In[1], the last sentence of the Abstract should read as follows: “Beyond 40-MHz offset from the local oscillator, the RX exhibits more than +23 dBm out-of-band third-order input intercept point (OB-IIP3) without FTNC and more than +26 dBm OB-IIP3 with FTNC.” In addition, the definition of OB-IIP3 in the last sentence of the fourth paragraph of Section I should be “out-of-band third-order input intercept point (OP-IIP3).”

A 100-MHz-2-GHz closed-loop analog in-phase/ quadrature correction circuit for digital clocks is presented. The proposed circuit consists of a phase-locked looptype architecture for quadrature error correction. The circuit corrects the phase error to within a 1.5° up to 1 GHz and to within 3° at 2 GHz. It consumes 5.4 mA from a 1.2 V supply at 2 GHz. The circuit was designed in UMC 0.13-μm mixed-mode CMOS with an active area of 102 μm×95 μm. The impact of duty cycle distortion has been analyzed. High-frequency quadrature measurement related issues have been discussed. The proposed circuit was used in two different applications for which the functionality has been verified.

A frequency domain capacitance interface system is proposed for a femto-farad capacitance measurement. In this technique, a ring oscillator circuit is used to generate a change in time period, due to a change in the sensor capacitance. The time-period difference of two such oscillators is compared and is read-out using a phase frequency detector and a charge pump. The output voltage of the system, is proportional to the change in the input sensor capacitance. The capacitance sensor interface system was designed and a prototype was implemented in a 0.13 μm standard CMOS technology. Experimental and simulation results are presented. It exhibits a maximum sensitivity of 8.1 mV/fF, which is significant improvement over the state-of-the-art while consuming 3.2 mW from a 1.2 V supply.

A wideband spectrum sensing system for cognitive radio is designed and implemented in a 130-nm radio frequency mixed-mode CMOS technology. The system employs an I-Q downconverter, a pair of complex filters, and a pair of envelope detectors to perform the spectrum sensing from 250 MHz to 3.25 GHz. The design makes use of the bandpass nature of the complex filter to achieve two objectives: 1) separation of upper sideband and lower sideband around the local oscillator signal and 2) resolution of smaller bands within a large detection bandwidth. The measured sensitivity is close to -45 dBm for a single tone test over a bandwidth of 40 MHz. The measured image reject ratio is close to 30 dB. The overall wideband detection bandwidth is 250 MHz, which is partitioned into 40-MHz narrowband chunks with eight such overlapping chunks.

A duty-cycle correction technique using a novel pulsewidth modification cell is demonstrated across a frequency range of 100 MHz-3.5 GHz. The technique works at frequencies where most digital techniques implemented in the same technology node fail. An alternative method of making time domain measurements such as duty cycle and rise/fall times from the frequency domain data is introduced. The data are obtained from the equipment that has significantly lower bandwidth than required for measurements in the time domain. An algorithm for the same has been developed and experimentally verified. The correction circuit is implemented in a 0.13-μm CMOS technology and occupies an area of 0.011 mm2. It corrects to a residual error of less than 1%. The extent of correction is limited by the technology at higher frequencies.