Calibration of a quantum computer is the process of optimizing its control parameters to ensure the accurate implementation of quantum gates.It remains a critical challenge in scaling quantum computers.Existing calibration methods take a generalized approach that focuses on the trade-off between calibration time and fidelity.However, these methods lack the awareness of hardware differences among physical qubits and an elaborate design of parallel calibration.In this paper, we introduce a fine-grained calibration protocol that contains three calibration policies for hardware differences and a method to enable parallel calibration.We begin by profiling qubit pairs to evaluate their responses to different waveform candidates.Based on profiling results, we determine the best calibration policy for the quantum computer, which is the first part of the calibration protocol.The second part of our protocol is to use graph traverse to enable parallel calibration by identifying compatible calibration operations.We validate our protocol through intensive experiments on real quantum machines with up to 127 qubits.Our experimental results demonstrate a 1.84× reduction in terms of the medium of the two-qubit gate error rate, 1.26× reduction in pulse duration, an 8× to 25× reduction in total calibration overhead compared with sequential calibration, an average of 2.12× further reduction in total calibration overhead owing to profiling policy, double of the quantum volume, and a 2.0× to 2.3× reduction in error per layered gate.The proposed protocol emphasizes the importance of hardware-aware and parallel calibration and advances current quantum computers towards fault-tolerant quantum computing.

In this paper, we examine the impact and significance of bias terms in Implicit Neural Representations (INRs). While bias terms are known to enhance nonlinear capacity by shifting activations in typical neural networks, we discover their functionality differs markedly in neural representation networks. Our analysis reveals that INR performance neither scales with increased number of bias terms nor shows substantial improvement through bias term gradient propagation. We demonstrate that bias terms in INRs primarily serve to eliminate \textit{spatial aliasing} caused by symmetry from both coordinates and activation functions, with input-layer bias terms yielding the most significant benefits. These findings challenge the conventional practice of implementing full-bias INR architecture. We propose using freezing bias terms exclusively in input layers, which consistently outperforms fully biased networks in signal fitting tasks. Furthermore, we introduce Feature-Biased INRs~(Feat-Bias), which initialize input-layer bias with high-level features extracted from pre-trained models. This feature-biasing approach effectively addresses the limited performance in INR post-processing tasks due to neural parameter uninterpretability, achieving superior accuracy while reducing parameter count and improving reconstruction quality.

The Quantum Approximate Optimization Algorithm (QAOA) is one of the most promising candidates for achieving quantum advantage over classical computers. However, existing compilers lack specialized methods for optimizing QAOA circuits. There are circuit patterns inside the QAOA circuits, and current quantum hardware has specific qubit connectivity topologies. Therefore, we propose Coqa to optimize QAOA circuit compilation tailored to different types of quantum hardware. Our method integrates a linear nearest-neighbor (LNN) topology and efficiently map the patterns of QAOA circuits to the LNN topology by heuristically checking the interaction based on the weight of problem Hamiltonian. This approach allows us to reduce the number of SWAP gates during compilation, which directly impacts the circuit depth and overall fidelity of the quantum computation. By leveraging the inherent patterns in QAOA circuits, our approach achieves more efficient compilation compared to general-purpose compilers. With our proposed method, we are able to achieve an average of 30% reduction in gate count and a 39x acceleration in compilation time across our benchmarks.