A D-band (114--170GHz) CMOS transceiver (TRX) chipset covering a 56GHz signal-chain bandwidth with a 640-Gb/s data rate is proposed in this work. The design includes an 8-way low-Q power-combined power amplifier (PA), a 2-way low-Q power-combined low noise amplifier (LNA), wideband-impedance-transformation mixers, and common-source-based cascaded distributed amplifiers (DA) to improve bandwidth and linearity. The proposed TRX chipset achieves a 200Gb/s SISO data rate and a 640Gb/s MIMO data rate.

A tri-mode mixer supporting the 5G NR standards over 24.25--71GHz is presented. The harmonic-selection technique reduces the local oscillator (LO) frequency range and power consumption. Besides, the proposed multiphase LO rejects unwanted harmonics. Fabricated in a 65nm CMOS process, this work consumes 12-21mW power under a 1V supply. It presents more than 20dB rejections to the undesired harmonic components at all operation bands. The required LO frequency range is only 10GHz.

An 8-Element 28-GHz time-division MIMO beamformer supporting 4x4 MIMO is presented. A fast-switching phase shifter is utilized to realize Nyquist-rate beam switching to lossless receive multiple beams by reuse single RF signal path. A prototype fabricated in 65nm CMOS achieves 64-QAM 4x4 MIMO reception in OTA measurement using four 5G NR spatial data streams with 400MHz channel bandwidth.

This paper presents a tri-mode band-selection CMOS down-conversion mixer supporting the 5G NR standards over 24.25–71 GHz. The harmonic-selection technique reduces the required local oscillator (LO) frequency range and power consumption. The second-harmonic selection mode works for the 39-GHz and 47-GHz bands, while the fundamental-selected and third-harmonic selection modes operate for the 28-GHz and 60-GHz bands, respectively. Besides, in cooperation with the proposed multi-phase LO, the mixing components behave destructively for the undesired harmonics and constructively for the desired component, which shows the rejection of unwanted harmonics. Fabricated in a 65-nm CMOS process, this work presents flat conversion gain and more than 20-dB rejections to the undesired harmonic components at all operation bands. The required LO frequency range is only 10 GHz. Occupying a core area of 0.0077 mm2, the proposed mixer consumes power of 12-21 mW in three modes under a 1-V supply.

This work first discusses the future directions of millimeter-wave wireless communication, based on Shannon and Friis equations. Afterward, 28-GHz and 39-GHz phased-array transceivers realized by 65nm CMOS technology are introduced, which are designed for 5G and beyond. The 28GHz phased- array transceiver is designed based on a neutralized bi-directional technique. The required chip area for the element transceiver is reduced to half. A cross-pol. leakage canceller is also implemented along with the transceiver to suppress the crosspol. leakage. Therefore, the dual-polarized 28-GHz phased-array module is capable to improve the wireless data with dual- polarized MIMO (DP-MIMO) configuration even under severe polarization coupling and rotation conditions. The measured DP-MIMO EVMs are 3.4% in both 64-QAM and 256-QAM. The 8-element 39GHz phased-array transceiver is also designed based on the compact bi-directional architecture. The Doherty technique is utilized in TX mode to increase the power efficiency at power backoff region. A 64-element transmitter array realizes a saturated output EIRP of 55.2dBm. To improve the phased- array performance under digital pre-distortion (DPD), an inter- element mismatch compensation technique is further employed. By utilizing the proposed mismatch compensation, the measured 64-QAM OFDMA-mode EVM and ACLR with the shared-look- up-table (shared-LUT) DPD are improved from -22.4dB to - 25.0dB and from -28.7dBc to -32.1dBc, respectively.

This article presents a small-area Bluetooth Low-Energy (BLE) transceiver (TRX) for short-range Internet-of-Things (IoT) applications in 65-nm CMOS. An integrated Radio-Frequency Input-Output (RFIO) circuitry embedded with transmitter/receiver (TX/RX) switch function and on-chip impedance matching is proposed. A hybrid-loop TRX structure based on a wide-bandwidth fractional-N digital phase-locked loop (DPLL) is implemented to achieve the maximum power reduction. A -94dBm receiver sensitivity is achieved with 2.3mW receiver power consumption, while a RF receiving bypass route integration enhances the input power tolerance. The BLE transceiver delivers -6dBm output power while consuming 2.6mW and delivers 0dBm output power while achieving 18.5% maximum TX efficiency. Thanks to the RFIO with harmonic suppression, -56dBc of 2nd-order harmonic distortion (HD2) and -48dBc of 3rd-order harmonic distortion (HD3) suppression are achieved with 0.85mm2on-chip area. This transceiver satisfied the BLE radio specification without the need for external filters and with low-power consumption, which enables minimum size and long life-time modules.

A 28GHz differential bi-directional amplifier in a standard 65nm CMOS process is presented. This work is realized based on the neutralized bi-directional core together with the fully shared inter-stage matching networks. The core chip area is only 0.11mm2. At 28GHz, a 15.1-dBm saturation output power and a 4.2-dB noise Figure are realized for PA mode and LNA mode, respectively. The DC power consumptions for PA mode and LNA mode are 149mW and 31mW, respectively, under 1-V DC supply.