We consider the implication of deep sub-micron VLSI technology on the design of communication frameworks for parallel DSP systems-on-chip. We assert that distributed data transfer and control mechanisms are necessary to manage many independent processing subsystems and software tasks. An example of a parallel DSP architecture is given and used to demonstrate these mechanisms at work. We show the similarity of these mechanism and those used in large scale computing networks.

In this paper, we describe the software environment for Daytona, a single-chip, bus-based, shared-memory, multiprocessor DSP.The software environment is designed around a layered architecture.Tools at the lower layer are designed to deliver maximum performance and include a compiler, debugger, simulator, and profiler.Tools at the higher layer focus on improving the programmability of the system and include a run-time kernel and parallelizing tools.The run-time kernel includes a low-overhead, preemptive, dynamic scheduler with multiprocessor support that guarantees real-time performance to admitted tasks.1.

This paper compares low power techniques current in the research literature with those used in commercial DSP design and explores why some techniques have not yet had commercial impact. It also examines the low power needs of future DSP applications.

An environment for the full-custom design of high-sample-rate digital signal processing (DSP) VLSI circuits is described. An overall design methodology that allows for tradeoffs between algorithms, architecture, and layout is presented. Key CAD tools used in this methodology include architecture mapping, generators, symbolic layout, clock network analysis, and timing simulation. These tools allow designers to move rapidly from specification to layout while keeping a close check on performance parameters such as speed and power dissipation. Two high-speed video chips that were designed using these techniques are described.>

An event-driven approach to MOS timing simulation is presented, which has proved to be more efficient and reliable than time-step-based methods. The MOS network is statically partitioned into groups of strongly coupled nodes called regions. Regions are scheduled for evaluation using a priority event queue. Events are predictions of the time at which nodes within a region will change by more than a voltage threshold. Region evaluation is performed using a single modeling step followed by linear relaxation. The simulator has been used to verify the timing and functionality of a number of large (>500 K transistors) VLSI chips. Performance is 2-5 times faster than time-step-based methods and 200-300 times faster than circuit simulation.>

Flute is a heuristic floorplanner that operates as one of the agents of the Cadre - a system of cooperating expert agents for converting a hierarchical structural description into full custom VLSI layout. Flute is modeled on the human floorplanning process and uses a mixture of rule-based programming, state control and algorithmic operators. Initially, a topological plan is generated by placing modules on a grid graph. From this plan, a constraint graph is prepared. This graph is solved in order to add geometric size and placement information to the floorplan.

Dynamic time warping is a well-established technique for time alignment and comparison of speech and image patterns. This paper decribes the architecture, algorithms, and design of a CMOS integrated processing array used for computing the dynamic time warp algorithm. Emphasis is placed on speech recognition applications because of the real-time constraints imposed by isolated and continuous speech recognition.

Dynamic time warping is an established technique for time alignment and comparison of speech segments in speech recognition. This paper describes a CMOS integrated array processor for computing the dynamic time warp algorithm. It allows many popular variations including LPC and frequency domain representations of speech. High speed is obtained by extensive pipelining, parallel computation, and simultaneous matching of multiple patterns. A realistic application using 40 nine-component LPC vectors per word permits 10,000 word comparisons per second or, equivalently, real time recognition of a 10,000 word vocabulary.

Contour (polygon) filling is a primitive required in many application areas of raster scan graphics. The bit-map memory in a frame-store display is computationally well suited to this task, as it provides a large scratch pad working space. In this paper, a number of contour filling algorithms based on the read/write properties of the frame-store memory are compared with the classical `ordered-edge-list' approach. Performance is evaluated on a microcomputer controlled frame-store display system in terms of ability to fill correctly, execution speed and processor memory requirements. A new algorithm, based on a more exact definition of an object edge, is presented. This algorithm, denoted edge flag algorithm, is implemented within the frame-store memory. It features high speed, in conjunction with minimal CPU memory requirements, making it ideally suited to hardware or microcode (firmware) implementation.

Raster-scan color graphic displays provide increased visual feedback in many CAD areas. In addition the unique architecture of displays used for this purpose enable other CAD related problems to be solved within the hardware structure of the display. Achieving these features commensurate with human response times requires new architecures and algorithm development for color displays.

A frame store display station capable of generating real time animation effects using filled polygonal shapes is described. The system consists of a host microcomputer, a high performance frame store display controller and a microprogrammed graphic command interpreter. Real time performance is attained using a combination of software, hardware and a systems approach. The display station can be used to interactively test and view simple animation sequences. Some proposals for further increasing performance are discussed.

Cache storage is a proven memory speedup technique in large mainframe computers. Two of the main difficulties associated with the use of this concept in small machines are the high relative cost and complexity of the cache controller. An LSI bit-slice chip set is described which should reduce both controller cost and complexity. The set will enable a memory designer to construct a wide variety of cache structures with a minimum number of components and interconnections. Design parameters are based on the results of extensive simulation. Particular emphasis is placed on the need for design flexibility.