Multithreading is an efficient technique commonly used to maximize the performance of CPU. One of the most important challenges in multithreading is thread pool management. It needs to retain a proper number of threads in the pool, which minimizes the response time and maximizes the resource utilization. To achieve this goal, this paper proposes a novel trendy exponential moving average (TEMA) scheme for predicting the number of threads. Also, a prediction-based thread pool management scheme is proposed which adjusts the idle timeout period and thread pool size to effectively adapt the system to the changing environment. The experiment results show the effectiveness of the proposed approach in terms of response time and CPU usage, compared with the existing prediction-based scheme and Sun watermark.

Today, mobile IPTV provides various multimedia services. Therefore, extensive researches on providing service continuity in the mobile IPTV environment are being conducted. Here reducing the user waiting time under the restriction of limited bandwidth is an important design issue in the video on-demand multicast service. In this paper we propose a scheme reducing the waiting time of a user wanting to start to view the video not from the beginning but from any point. The proposed scheme allows significantly reduced waiting time compared to the existing scheme for varying request rates and number of channels, as verified by computer simulation.

In this paper, we provide a low cost AES core for ZigBee devices which accelerates the computation of AES algorithms. Also, by embedding the AES core, we present an efficient architecture of security accelerator satisfying the IEEE 802.15.4 specifications. In our experiments, we observed that the AES core and the security accelerator use fewer logic gates and consume lower power than other architectures based on block-wide and folded ones.

Digitalization of various kinds of information is accelerating the convergence between them by fast development of network technology. Service provision also has been advanced because the convergence of information is becoming easy. And there are many researches to realize context-aware services that recognize users and devices environments based on context-aware computing technology in order to provisioning the intelligent service. In this paper, we show a variety of context information of device, network, user, position, and mobility in heterogeneous networks based on IMS (IP multimedia subsystem) and present structure and function of context-aware system for IMS service enabler. The context-aware system decides appropriate services that are the most suitable according to circumstance information in the Ontology.

In general, the cryptographic operation in wireless devices which have low memory and low computing power causes the system overhead, so that it badly affects the performance of other tasks. Therefore, it is positively necessary to implement the security hardware which is dedicated to the cryptographic operation. Early researches about the security hardware architectures make design metrics with data throughput, gate usage, and power consumption to demonstrate the efficiency of their architectures. In this paper, we provide an efficient hardware architecture of the security processing for ZigBee, which satisfies the constraints IEEE 802.15.4 standard requires. These requirements mainly consist of the critical response time, the verification delay, and the throughput. In experiments, we implemented the security processing for ZigBee that used fewer logic gates and consumed low power than other earlier ZigBee chips and fulfilled the standard requirements with considerable margins.

The authors point out that significant improvements in the speed of fault simulation of combinational circuits have been achieved in recent years by combining parallel pattern simulation for the fault-free circuit with trace-based methods for identifying detected faults. Here, two concepts-joining stems for reducing explicit simulation of stem faults and quit lines for reducing backtracing within fanout-free regions-are presented. These concepts are used in a parallel-pattern trace-based simulation algorithm. Results of simulating the ISCAS85 benchmark combinational circuits with the proposed methods show their effectiveness both with and without fault-dropping.>

An efficient fault simulation algorithm for synchronous sequential circuits is presented. It uses parallel fault simulation with dynamic fault grouping, and combines it with backtracing within certain fanout-free regions and the use of surrogate faults. A backtracing method is developed to handle the three logic values, 0,1, and X, accurately. The concept of surrogate faults is also extended to represent all nine combinations of fault-free and faulty values. The results of simulating a set of benchmark sequential circuits show that reductions in execution time of 7-54% were obtained by the use of backtracing and surrogate faults compared to the well-known method, PROOFS.>

Significant improvements in the speed of fault simulation of combinational circuits have been achieved by combining parallel pattern simulation of the fault-free circuit with tracing-based methods for identifying detected faults. The authors propose a method of reducing the expense of backtracing by identifying lines where backtracking may be stopped, and they show its efficiency through an experiment with a set of benchmark circuits. The proposed method has been implemented in the C language on a VAX 6210/VMS which has a machine word of 32 b. Thirty-two patterns are processed in parallel during true-value simulation, backtracing, and stem analysis. Calculations of the sensitivity, stem-criticality, and checkup vectors are performed by vector operations when each line is reached during first backtracing. The results indicate that the proposed method is more efficient than that of K.J. Antreich and M.H. Schultz (1987) for all the benchmark circuits that were simulated.>