Heterogeneous multicore processors have recently become de facto computing engines for state-of-the-art embedded applications. Nonetheless, very little research focuses on the scheduling of periodic (implicit-deadline) real-time tasks upon heterogeneous multicores under the requirements of task synchronization, which is stemmed from resource access conflicts and can greatly affect the schedulability of tasks. In view of partitioned Earliest Deadline First and Multiprocessor Stack Resource Policy, we first discuss the blocking-aware utilization bound for uniform heterogeneous multicores and then illustrate its non-monotonicity, where the bound may decrease with more deployed cores. Following the insights obtained from the bound analysis, taking the system heterogeneity into consideration, we propose a Synchronization-Aware Task Partitioning Algorithm for Heterogeneous Multicores (SA-TPA-HM)). Several resource-guided and heterogeneity-oriented mapping heuristics are incorporated to reduce the negative impacts of blocking interferences for better schedulability performance of tasks and balanced workload distribution across cores. The extensive simulation results show that SA-TPA-HM can obtain the schedulability ratios approximate to an Integer Non-Linear Programming--based solution, and much higher (e.g., 60% more) in contrast to the existing partitioning algorithms targeted at homogeneous multicores. The measurement results in Linux kernel further reveal the practical viability of SA-TPA-HM that can experience lower runtime overhead (e.g., 15% less) when compared to other mapping schemes.

Heterogeneous multicore processors have become popular computing engines for modern embedded real-time systems recently. However, there is rather limited research on the scheduling of real-time tasks running on heterogeneous multicore systems with shared resources. Note that, different partitionings of tasks upon heterogeneous cores can affect the synchronization overheads of tasks (and thus the system schedulability). Focusing on the partitioned-EDF scheduling and resource access protocol MSRP (Multiprocessor Stack Resource Policy), this paper proposes an effective synchronization aware task partitioning algorithm for heterogeneous multicores (SATPA-HM). Several resource-oriented heuristics are exploited to tighten the bound on the synchronization costs of tasks through dynamic task prioritization and to find an appropriate core for each task that can minimize the system utilization increment. The simulation results show that our proposed SA-TPA-HM scheme can achieve higher acceptance ratio (e.g., 60% more), when compared to the existing schemes designed for homogeneous multicores.

This paper presents an integrated multi-port converter(IMPC) for Switched Reluctance Machine (SRM). The conventional drive for SRM is based on asymmetrical H-bridge which needs a large capacitor on the dc bus to absorb the transient energy caused by turn-off process. The proposed topology is a multi-port converter which employs the capacitor as an extra port to the dc bus and is integrated based on switch multiplexing. With such converter, the capacitance can be reduced significantly by increasing the capacitor voltage ripple. In addition, the current commutation process can be accelerated with high voltage of capacitor based on such topology. The requirement of capacitance in asymmetrical H-bridge and the proposed topology is analyzed in detail and the corresponding control method for the proposed converter is introduced briefly as well. Simulation results in Matlab/Simulink verified the feasibility of the proposed topology and its superior performance compared with asymmetrical H-bridge structure.

This paper proposes a three-phase grid impedance detection method based on dual-frequency harmonic current injection for islanding detection. Grid impedance detection based on single harmonic current injection is reliable in three-phase impedance balanced grid. However, under impedance unbalanced condition, the harmonic voltage caused by the injected symmetric harmonic current is asymmetric, which affects the calculation of grid impedances and even leads to failed detection. The method based on dual-frequency harmonic current injection is injecting two non-characteristic symmetric harmonic currents, and then according to the different harmonic voltages caused by different frequency harmonic currents, all three-phase impedances can be calculated accurately. The implementing algorithm of the presented method is derived and its performance is analyzed in detail. Simulation and experiments are carried out under grid impedance balanced and unbalanced conditions. Theoretical analysis and experiment results proved that the proposed method is feasible.