With ever increasing network traffic rates, multicore architectures for network processors have successfully provided performance improvements through high parallelism. However, naively allocating the network traffic to multiple cores without considering diversified applications and flow locality results in issues such as packet reordering, load imbalance and inefficient cache usage. Consequently, these issues degrade the performance of latency sensitive network processors by dropping packets or delivering packets out of order. In this paper, we propose a packet scheduling scheme that considers the multiple dimensions of locality to improve the throughput of a network processor while minimizing out of order packets. Our scheduling policy tries to maintain packet order my maintaining the flow locality, minimizes the migration of flows from one core to another by identifying the aggressive flows, and partitions the cores among multiple services to gain instruction cache locality. Our light weight hardware implementation shows improvement of 60 percent in the number of packets dropped and 80 percent in the number of out-of-order packet deliveries over previously proposed techniques.

We present a novel automated multicore benchmark synthesis framework with characterization and generation components. Our framework uses parallel patterns in capturing important characteristics of multi-threaded applications and generates synthetic multicore benchmarks from those applications. The resulting synthetic benchmarks are small, fast, portable, human-readable, and they accurately reflect microarchitecture dependent and independent characteristics of the original multicore applications. Also, they can use either Pthreads or MCA libraries. We implement our techniques in the MINIME tool and generate synthetic benchmarks from PARSEC, Rodinia, and EEMBC MultibenchTM benchmarks on x86 and Power Architecture®platforms. We show that synthetic benchmarks are representative across a range of multicore machines with different architectures, while being on average 21× faster and 14× smaller than original benchmarks.

In the many-core era, scalable coherence and on-chip interconnects are crucial for shared memory processors. While snoopy coherence is common in small multicore systems, directory-based coherence is the de facto choice for scalability to many cores, as snoopy relies on ordered interconnects which do not scale. However, directory-based coherence does not scale beyond tens of cores due to excessive directory area overhead or inaccurate sharer tracking. Prior techniques supporting ordering on arbitrary unordered networks are impractical for full multicore chip designs.

This paper introduces a new architectural technique called asymmetric scaling on heterogeneous multi-core network processor architectures to mitigate the problem of dark silicon in future process technologies. In asymmetric scaling, the number of low power cores is increased at a higher rate than the number of high performance cores over process generations. Using an analytical model we show that coupled with fixed voltage-frequency scaling, asymmetric scaling can maintain the power density of the chip at the same level for several process generations, while increasing computational capabilities according to Dennardian scaling. Asymmetric scaling aligns nicely with the application characteristics on a network packet processor. To illustrate the concept, we discuss the Layerscape network processor architecture that incorporates a general purpose layer of high performance cores with an accelerated packet processing layer of low power cores. We discuss several techniques that can be applied to reduce the power density of low power cores. Using a representative packet forwarding workload, we show that shallow-pipeline, dual-issue, in-order cores with appropriate hardware acceleration and limited on-chip memory are a good choice for the low power processor layer.

With ever increasing network traffic rates, multicore architectures for network processors have successfully provided performance improvements through high parallelism. However, naively allocating the network traffic to multiple cores without considering diversified applications and flow locality results in issues such as packet reordering, load imbalance and inefficient cache usage. Consequently, these issues degrade the performance of latency sensitive network processors by dropping packets or delivering packets out of order. In this paper, we propose a packet scheduling scheme that considers the multiple dimensions of locality to improve the throughput of a network processor while minimizing out of order packets. Our scheduling policy tries to maintain packet order by maintaining the flow locality, minimizes the migration of flows from one core to another by identifying the aggressive flows, and partitions the cores among multiple services to gain instruction cache locality. The scheduler uses a novel low cost two-level caching scheme to identify top aggressive flows. Our light weight hardware implementation shows improvement of 60% in the number of packets dropped and 80% improvement in the out-of-order packet deliveries over previously proposed techniques.

Multicore embedded systems are being widely used in telecommunication systems, robotics, medical applications and more.While they offer a high-performance with low-power solution, programming in an efficient way is still a challenge. In order to exploit the capabilities that the hardware offers, software developers are expected to handle many of the low-level details of programming including utilizing DMA, ensuring cache coherency, and inserting synchronization primitives explicitly. The state-of-the-art involves solutions where the software toolchain is too vendor-specific thus tying the software to a particular hardware leaving no room-for portability.

Addressing the challenges of extreme scale computing requires holistic design of new programming models and systems that support those models. This paper discusses the Angstrom processor, which is designed to support a new Self-aware Computing (SEEC) model. In SEEC, applications explicitly state goals, while other systems components provide actions that the SEEC runtime system can use to meet those goals. Angstrom supports this model by exposing sensors and adaptations that traditionally would be managed independently by hardware. This exposure allows SEEC to coordinate hardware actions with actions specified by other parts of the system, and allows the SEEC runtime system to meet application goals while reducing costs (e.g., power consumption).

Verification of embedded multicore applications is crucial as these applications are deployed in many safety critical systems. Verification task is complicated by concurrency inherent in such applications. We use mutation testing to obtain a quantitative verification coverage metric for mullticore applications developed using the new Multicore Communication API (MCAPI) standard. MCAPI is a lightweight API that targets heterogeneous multicore embedded systems. We developed a mutation coverage tool and performed several experiments on MCAPI applications. Our experiments show that mutation coverage is useful in measuring and improving the quality of the test suites and ultimately the quality of the multicore application.

We describe verification and coverage methods for multicore software that uses message passing libraries for communication. Specifically, we provide techniques to improve reliability of software using the new industry standard MCAPI by the Multicore Association. We develop dynamic predictive verification techniques that allow us to find actual and potential errors in a multicore software. Some of these error types are deadlocks, race conditions, and violation of temporal assertions. We complement our verification techniques with a mutation-testing-based coverage metric. Coverage metrics enable measuring the quality of verification tests. We implemented our techniques in tools and validated them on several multicore programs that use the MCAPI standard. We implement our techniques in tools and experimentally show the effectiveness of our approach. We find errors that are not found using traditional dynamic verification techniques and we can potentially explore execution schedules different than the original program with our coverage tool. This is the first time such predictive verification and coverage metrics have been developed for MCAPI.

Multicore Systems-on-Chip (MCSoC) are comprised of a rich set of processor cores, specialized hardware accelerators, and I/O interfaces. Functional verification of these complex designs is a critical and demanding task, however, focusing only on functional verification is very risky because the motivation for building such systems in the first place is to achieve high levels of system throughput. Therefore a functionally correct MCSoC that does not exhibit sufficient performance will fail in the market. In addition, limiting performance verification efforts to analyzing individual system components in isolation is insufficient due to: (1) the degree of system-level resource contention that an application domain imposes on the MCSoC, and (2) the degree of configuration flexibility that is typically afforded by an MCSoC. These factors motivate system-level performance verification of MCSoC. This article presents an important industrial case study of MCSoC performance verification involving both pre- and postsilicon analysis, highlighting the methodology used, the lessons learned, and recommendations for improvement.

We present a dynamic verification tool MCC for Multicore Communication API applications - a new API for communication among cores. MCC systematically explores all relevant interleavings of an MCAPI application using a tailor-made dynamic partial order reduction algorithm (DPOR). Our contributions are (i) a way to model the non-overtaking message matching relation underlying MCAPI calls with a high level algorithm to effect DPOR for MCAPI that controls the lower level details so that the intended executions happen at runtime; and (ii) a list of default safety properties that can be utilized in the process of verification. To our knowledge, this is the first push button model checker for MCAPI application writers that, at present, deals with an interesting subset of MCAPI calls. Our result is the demonstration that we can indeed develop a dynamic model checker for MCAPI that can directly control the non-deterministic behavior at runtime that is inherent in any implementation of the library without additional API modifications or additions.

The structure of a software architecture strongly influences the architecture's ability to prescribe systems satisfying functional requirements, non functional requirements, and overall qualities such as maintainability, reusability, and performance. Achieving an acceptable architecture requires an iterative derivation and evaluation process that allows refinement based on a series of tradeoffs. Researchers at the University of Texas at Austin are developing a suite of processes and supporting tools to guide architecture derivation from requirements acquisition through system design. The various types of decisions needed for concurrent derivation and evaluation demand a synthesis of evaluation techniques, because no single technique is suitable for all concerns of interest. Two tools in this suite, RARE and ARCADE, cooperate to enable iterative architecture derivation and architecture property evaluation. RARE guides derivation by employing a heuristics knowledge base, and evaluates the resulting architecture by applying static property evaluation based on structural metrics. ARCADE provides dynamic property evaluation leveraging simulation and model-checking. This paper presents a study whereby RARE and ARCADE were employed in the early stages of an industrial project to derive a Domain Reference Architecture (DRA), a high-level architecture capturing domain functionality, data, and timing. The discussion emphasizes early evaluation of performance qualities, and illustrates how ARCADE and RARE cooperate to enable iterative derivation and evaluation. These evaluations influenced DRA refinement as well as subsequent design decisions involving application implementation and computing platform selection.

Architectures embody the requirements expressed by system stakeholders, and the type of architecture used to capture a given set of requirements dictates when evaluation can occur and what will be evaluated. This research aims to leverage requirements and a resulting architecture dictated by the problem domain and captured early in the lifecycle. Thus, the research goal is to provide early performance evaluation in an effort to convey the most accurate blueprint to system implementers specifically and system stakeholders in general. A new software architecture evaluation tool called Arcade, developed to support the Systems Engineering Process Activities (SEPA), automates early performance evaluation of software architectures using simulation. SEPA suggests a comprehensive approach to capture and represent different types of requirements as a multi-level software architecture. One SEPA architecture level, the Domain Reference Architecture (DRA) encompasses performance characteristics inherent to the domain in terms of what processes, data, and timing are required, rather than how a system should be implemented. Performance evaluation of a DRA can provide qualitative data to (1) aid in identification and validation of domain related performance concerns, and (2) provide system implementers with performance guidelines towards satisfying the performance constraints inherent to the domain. The range of performance statistics Arcade is capable of analyzing is demonstrated through a case study of a Motorola e-business project.

The benefits of evaluating properties of software architectures stem from two important software architecture roles: (1) providing an opportunity to evaluate requirements and correct defects prior to implementation; and (2) serving as a blueprint for system developers. The paper focuses on a new software architecture evaluation tool called Architecture Analysis Dynamic Environment (Arcade) that uses model checking to provide software architecture safety and liveness evaluation during the requirements gathering and analysis phase. Model checking requires expertise not typically held by systems analysts and software developers. Thus, two barriers to applying model checking must be addressed: (1) translation of the software architecture specification to a form suitable for model checking, and (2) interpretation of the results of model checking. Arcade provides an automated approach to these barriers, allowing model checking of software architectures to be added to the list of techniques available to software analysts and developers focusing on requirements gathering and analysis.