Presents a fuzzy method for classification and recognition of separated handwritten characters. Linguistic expressions describing the individual characters are derived from a fuzzy model of a set of character samples. A small scale application of the method in which 26 lower-case cursive characters written by 30 different writers were analysed yielded 64% recognition rate. The method was also used to implement a character recogniser in a system for off-line recognition of cursive handwriting. In such a context, thanks to the use of a dictionary and a grammar parser, the recognition rate (at character level) rose to 96%.

Multiple processor architectures can be used to speed up the execution of logic programs, as they allow the exploitation of appropriate forms of OR–AND parallelism. In this paper we refer to distributed systems in which nodes are connected by means of point-to-point links, and information exchanges between processes are accomplished by message passing alone. The number of nodes is supposed to be not too large, and the memory of each node not sufficient to store all the database. A parallel interpreter for logic programs is proposed in which the parallelism exploited is not the maximum one and consists of the classical OR parallelism paired with an appropriate form of AND parallelism (‘backtracking parallelism’). The solutions are evaluated in the same order as a classical sequential depth-first interpreter.

The problem of implementing abstract objects in a system having a capability based addressing is analysed in some detail. Hardware features needed to support a classical capability environment are first pointed out, and a simple implementation of abstract objects is presented. Then a generalization of the classical capability environment is given, which allows one to solve the stated problem in a more efficient way.

Abstract In this paper a capability addressing environment is presented, based on the concept of extended capability. First of all it is shown that such an environment is well suited for implementing objects of abstract type. Then the problem of distributing and revoking access authorizations on abstract objects is considered and an efficient solution is presented. The revocation mechanism results in being selective, transitive and deferred.

In this work the generalized discrete Fourier transform (GFT), which includes the DFT as a particular case, is considered. Two pairs of fast algorithms for evaluating a multidimensional GFT are given (T-algorithm, F-algorithm, and T′-algorithm, F′-algorithm). It is shown that in the case of the DFT of a vector, the T-algorithm represents a form of the classical FFT algorithm based on a decimation in time, and the F-algorithm represents a form of the classical FFT algorithm based on decimation in frequency. Moreover, it is shown that the T′-algorithm and the T-algorithm involve exactly the same arithmetic operations on the same data. The same property holds for the F′-algorithm and the F-algorithm. The relevance of such algorithms is discussed, and it is shown that the T′-algorithm and the F′-algorithm are particularly advantageous for evaluating the DFT of large sets of data.

In this paper we present a new algorithm for evaluating the frequency F of a complex signal, represented by a rotating vector. We consider the two components of the signal on the real and on the imaginary axis, and we suppose we have for each component a sequence of N samples uniformly spaced at intervals T. Each sample represents a value of the pertinent component of the signal corrupted by noise, and the noise is assumed to be an ergodic stochastic process having a Gaussian distribution. The presented algorithm is much less complex compared to existing algorithms, such as the FFT (in fact it requires 8N - 17 additions and two divisions to be performed). Because of the noise, the computed frequency is affected by erros. The error distribution is evaluated by simulation. It is found that the error mean is practically equal to 0, while, for signal to noise ratios of 6-12 dB, the error variance is of the order of 0.1-0.001 times the quantity 1/T. If compared with a similar algorithm previously presented for computing the frequency of a real sinewave [4], the algorithm presented here gives results that are 5-10 times more accurate.

The structure of the Processing Element (PE), which is the basic component of SMA1, is presented. The PE consists of a simple serial arithmetic unit, a local high speed data memory, serial input and output ports, serial communication channels with neighbouring PE's, and some local control logic. The PE array operates under the control of a microprogrammed Array Control Unit (ACU). The peculiarities of ACU microprogramming are discussed, and some typical microprograms are reported. After presentation of the SMA principal instructions, some application programs are described implementing common radar filtering algorithms.

In this correspondence the problem of performing the multiplication by recoding the multiplier is considered. A special recoding for fractional numbers in two's complement form is presented, that generates a class of uniform shift multiplication algorithms having the property that every partial product is always in the open interval (-1,1). Both the scan of the multiplier from the least to the most significant bit and the scan in the opposite direction are considered.

The synchronous procedure and the asynchronous procedure for the synthesis of a master-slave circuit are examined. It is shown that the synchronous procedure leads to a circuit operating in fundamental mode, while the asynchronous procedure can be performed by taking into account the synchronous flow table. In both cases the same circuit is obtained.

Traditionally, synchronous sequential circuits are considered controlled by input pulses, and asynchronous sequential circuits by input levels. The aim of this note is to study the general properties of a class of asynchronous circuits with some inputs that can be thought of as driven by "pulses." The synthesis process and the internal structure of these circuits, called pulse input asynchronous sequential circuits (PA circuits), are investigated, and they are compared with pulse input synchronous circuits and with level input asynchronous circuits. Procedures are described to transform any flow table describing a synchronous circuit into a flow table describing an equivalent PA circuit, and to realize any normal mode asynchronous circuit by a PA circuit. Specific techniques for PA circuit state reduction and PA circuit state assignment are described in other papers.

Methods to realize race-free asynchronous sequential circuits by using appropriate single transition time (STT) state assignments have been described in the literature. This paper deals with that restricted class of asynchronous circuits (called pulse-input asynchronous circuits) for which in every input sequence each input state liis always followed by a special input state lo≠li. A method is presented to realize any pulse-input asynchronous sequential circuit with p internal states by a universal race-free STT state assignment in 2Eovariables, where Eo=[log2n] and n≤p is the number of the elements in a defined subset of internal states.