EDBT 2026 Demo / reviewers in the wild / expert
JIanDe Yu
dblp:10/2566
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 2009
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design › routing
FPGA routing |
0.1 | 1 | 2009 | A novel minloop SB design to improve FPGA routability · FPGA 2009 |
Electronic design automation
physical design |
0.1 | 1 | 2009 | A novel minloop SB design to improve FPGA routability · FPGA 2009 |
Electronic design automation › physical design › routing › routability
routability optimization |
0.1 | 1 | 2009 | A novel minloop SB design to improve FPGA routability · FPGA 2009 |
Electronic design automation › physical design › routing › FPGA routing
switch box design |
0.1 | 1 | 2009 | A novel minloop SB design to improve FPGA routability · FPGA 2009 |
Methods — techniques the papers use, named apart from their topics
minimum-loop-size maximization · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2009 | A novel minloop SB design to improve FPGA routabilityabstractIn this paper, we present a new design of a switch box of an FPGA that requires less channel width than conventional designs in routing the same circuit. The design, called a Minloop switch box, is based on the method of minimum-loop-size maximization in routing resources. Experimental results show that the Minloop switch box requires 17.7%, 8.0% and 2.4% less channel width than the classic fabric of Disjoint, Universal and Wilton switch boxes, respectively. JIanDe Yu, Jinmei Lai 0001 |
FPGA | 1 |