Emerging Internet of Things (IoT)-enabled cyber-physical applications, such as autonomous critical infrastructure inspection, demand low-latency, energy-efficient, and reliable execution across resource-constrained edge devices with heterogeneous multicore processors and diverse sensing and actuating capabilities, in collaboration with a hub device and a cloud server. These workflow-based applications comprise interdependent tasks that must be executed under stringent deadline, reliability, capability, memory, storage, and energy constraints. Given their critical nature, exact optimization is necessary to obtain optimal schedules that ensure dependable operation. Existing scheduling approaches, both exact and heuristic, fail to jointly address all these objectives and constraints. To this end, we propose an exact multi-objective and multi-constrained workflow scheduling approach for edge-hub-cloud cyber-physical systems, based on continuous-time mixed integer linear programming. The proposed formulation jointly optimizes latency, energy, and reliability, while holistically addressing timing and resource constraints. To enhance reliability while avoiding the overhead of unnecessary task replicas, it selectively employs task duplication. We evaluate our approach against a widely used heuristic, which we extend to ensure a fair and meaningful comparison, using a real-world IoT workflow and synthetic task graphs of varying sizes, across different system configurations and objective trade-offs. The proposed method consistently outperforms the heuristic, achieving up to 29.83%, 33.96%, and 28.49% average improvements in latency, energy, and reliability, respectively, while attaining practical runtimes. Overall, the experimental results demonstrate the effectiveness of our approach under various system configurations and objective trade-offs, and show its practical scalability to task graphs of sizes relevant to the targeted applications and system architecture.

To address the challenges of imbalanced multi-class datasets typically used for rare event detection in critical cyber-physical systems, we propose an optimal, efficient, and adaptable mixed integer programming (MIP) ensemble weighting scheme. Our approach leverages the diverse capabilities of the classifier ensemble on a granular per class basis, while optimizing the weights of classifier-class pairs using elastic net regularization for improved robustness and generalization. Additionally, it seamlessly and optimally selects a predefined number of classifiers from a given set. We evaluate and compare our MIP-based method against six well-established weighting schemes, using representative datasets and suitable metrics, under various ensemble sizes. The experimental results reveal that MIP outperforms all existing approaches, achieving an improvement in balanced accuracy ranging from 0.99% to 7.31%, with an overall average of 4.53% across all datasets and ensemble sizes. Furthermore, it attains an overall average increase of 4.63%, 4.60%, and 4.61% in macro-averaged precision, recall, and F1-score, respectively, while maintaining computational efficiency.

Machine learning inference deployed on edge devices is subject to limited resources, which pushes for better energy and resource efficiency, while ensuring high performance. At the algorithmic level, dynamic Deep Neural Networks (dDNNs) have been proposed in an effort to improve performance and energy efficiency which is particularly useful in time-critical systems such as autonomous navigation and search and rescue operations. These systems are often deployed in harsh environments, making the hardware vulnerable to soft errors. This work investigates the reliability of such dDNNs, specifically convolutional, focusing on early exit approaches, in an effort to better comprehend the impact of the early exits on the overall reliability of dDNNs. We consider transient faults and use hardware-aware software fault models, combined with a fine-grained fault taxonomy, to derive failures-in-time (FIT) rate and assess reliability. We observe a new category of faults specific to dDNNs and we refer to them as non-materialized faults. In our assessment, we use a new fault taxonomy that is more fine-grained than existing ones, also including the new category of non-materialized faults. We explore various early exit scenarios, having as baseline the Google Inception V1 network deployed on an NVDLA accelerator to generate FIT rates and analyze the faults per network architecture block and operation type. Furthermore, we investigate the impact of faults on the overall performance (accuracy) and execution time (average inference time) of the neural network models. Based on our analysis we observe that the overall FIT rate remains similar among different early exit implementations (8.40-8.89), while the distribution of the critical faults is influenced by the network’s design-time decisions on early exit block placement and architecture.

Unmanned Aerial Vehicles (UAVs) have become essential in search and rescue operations, especially in disaster management scenarios. Their effective navigation and the integration of a plethora of sensors assist in efficient person detection, making them an essential technological tool to first responders. Multi-UAV systems extend these benefits by using coordinated strategies to cover large areas efficiently, reducing overall mission response time and enhancing its success. Despite these advantages, challenges remain in ensuring the safety, security, and dependability of (mutli-)UAV missions. Issues such as navigation risks, potential cyber threats, and hardware-/software-related reliability issues can impact the mission results. Additionally, UAVs are highly constrained devices with limited battery capacity, requiring the use of lightweight technologies. In this paper, we present part of the results of the SESAME project, an EU multi-partner project that aims to develop safe and secure multi-robot Systems. In particular, we present some of the developed SESAME Executable Digital Dependability Identities (EDDI) technologies based on Markov models, statistical distance measures, and other advanced approaches for enhancing safety, security and dependability of the UAV platform and underlying models. These EDDI technologies are seamlessly integrated using the ConSerts framework in a multi-UAV platform and tested using search and rescue scenarios. The results demonstrate significant improvements in multi-UAV safety, with an availability rate of 91% and a search and rescue algorithmic accuracy of 99.8%. Additionally, the system achieves precise detection of spoofing attacks, using collaborative localization as a mitigation technique to guide the UAV to a safe landing, even in the absence of GPS signals,

Modern power systems face significant challenges in state estimation and real-time monitoring, particularly regarding response speed and accuracy under faulty conditions or cyber-attacks. This article proposes a hybrid approach using physics-informed neural networks (PINNs) to enhance the accuracy and robustness of power system state estimation. By embedding physical laws into the neural network architecture, PINNs improve estimation accuracy for transmission grid applications under both normal and faulty conditions, while also showing potential in addressing security concerns, such as data manipulation attacks. Experimental results show that the proposed approach outperforms traditional machine learning models, achieving up to$\sim$83% higher accuracy on unseen subsets of the training dataset and$\sim$65% better performance on entirely new, unrelated datasets. Experiments also show that during a data manipulation attack against a critical bus in a system, the PINN can be up to$\sim$93% more accurate than an equivalent neural network.

This paper presents a review of state-of-the-art solutions concerning the optimization of computing in the field of parallel and distributed systems. Firstly, we contribute by identifying resources and quality metrics in this context including servers, network interconnects, storage systems, computational devices as well as execution time/performance, energy, security, and error vulnerability, respectively. We subsequently identify commonly used problem formulations and algorithms for integer linear programming, greedy algorithms, dynamic programming, genetic algorithms, particle swarm optimization, ant colony optimization, game theory, and reinforcement learning. Afterward, we characterize frequently considered optimization problems by stating these terms in domains such as data centers, cloud, fog, blockchain, high performance, and volunteer computing. Based on the extensive analysis, we identify how particular resources and corresponding quality metrics are considered in these domains and which problem formulations are used for which system types, either parallel or distributed environments. This allows us to formulate open research problems and challenges in this field and analyze research interest in problem formulations/domains in recent years.

The emerging edge-hub-cloud paradigm has enabled the development of innovative latency-critical cyber-physical applications in the edge-cloud continuum. However, this paradigm poses multiple challenges due to the heterogeneity of the devices at the edge of the network, their limited computational, communication, and energy capacities, as well as their different sensing and actuating capabilities. To address these issues, we propose an optimal scheduling approach to minimize the overall latency of a workflow application in an edge-hub-cloud cyber-physical system. We consider multiple edge devices cooperating with a hub device and a cloud server. All devices feature heterogeneous multicore processors and various sensing, actuating, or other specialized capabilities. We present a comprehensive formulation based on continuous-time mixed integer linear programming, encapsulating multiple constraints often overlooked by existing approaches. We conduct a comparative experimental evaluation between our method and a well-established and effective scheduling heuristic, which we enhanced to consider the constraints of the specific problem. The results reveal that our technique outperforms the heuristic, achieving an average latency improvement of 13.54% in a relevant real-world use case, under varied system configurations. In addition, the results demonstrate the scalability of our method under synthetic workflows of varying sizes, attaining a 33.03% average latency decrease compared to the heuristic.

Connected and Autonomous Vehicles (CAV) depend on satellite systems, such as the Global Positioning System (GPS), for location awareness. Location data are streamed in real-time to the CAV’s perception engine from its onboard GPS receiver for autonomous driving and navigation. However, these receivers are vulnerable to location spoofing attacks that can be easily launched using Commercial-Off-The-Self (COTS) equipment and open-source software. Existing data-driven attack detection solutions typically require data associated with ‘normal’ and ‘attack’ labels. The latter are hard to collect in operational conditions or even in controlled experiments. To this end, we formulate the GPS location spoofing attack detection as an outlier detection problem. The proposed solution based on Machine Learning (ML) relies solely on normal location data for training during attack-free operation. Our solution demonstrates more than 98% detection accuracy according to standard metrics on realistic data produced with the CARLA driving simulator and outperforms by 15% another (non ML-based) state-of-the-art solution.

Embedded systems in critical domains, such as auto-motive, aviation, space domains, are often required to guarantee both functional and temporal correctness. Considering transient faults, fault analysis and mitigation approaches are implemented at various levels of the system design, in order to maintain the functional correctness. However, transient faults and their mitigation methods have a timing impact, which can affect the temporal correctness of the system. In this work, we expose the functional and the timing implications of transient faults for critical systems. More precisely, we initially highlight the timing effect of transient faults occurring in the combinational and sequential logic of a processor. Furthermore, we propose a full stack vulnerability analysis that drives the design of selective hardware-based mitigation for real-time applications. Last, we study the timing impact of software-based reliability mitigation methods applied in a COTS GPU, using a fault tolerant middleware.

Firmware refers to device read-only resident code which includes microcode and macro-instruction -level routines. For Internet-of-Things (IoT) devices without an operating system, firmware includes all the necessary instructions on how such embedded systems operate and communicate. Thus, firmware updates are an essential part of device functionality. They provide the ability to patch vulnerabilities, address operational issues, and improve device reliability and performance during the lifetime of the system. This process, however, is often exploited by attackers in order to inject malicious firmware code into the embedded device. In this paper, we present a framework for secure firmware updates on embedded systems. The approach is based on hardware primitives and cryptographic modules, and it can be deployed in environments where communication channels might be insecure. The implementation of the framework is flexible as it can be adapted in regards to the IoT device's available hardware resources and constraints. Our security analysis shows that our framework is resilient to a variety of attack vectors. The experimental setup demonstrates the feasibility of the approach. By implementing a variety of test cases on FPGA, we demonstrate the adaptability and performance of the framework. Experiments indicate that the update procedure for a 1183kB firmware image could be achieved, in a secure manner, under 1.73 seconds.

introduction Share on Introduction to the Special Issue on Hardware-Assisted Security for Emerging Internet of Things Editors: Saraju P. Mohanty University of North Texas University of North TexasView Profile , Jim Plusquellic University of New Mexico University of New MexicoView Profile , Garrett S. Rose University of Tennessee, Knoxville University of Tennessee, KnoxvilleView Profile , Wei Zhang Hong Kong University of Science and Technology Hong Kong University of Science and TechnologyView Profile , Maria K. Michael University of Cyprus University of CyprusView Profile Authors Info & Claims ACM Journal on Emerging Technologies in Computing SystemsVolume 18Issue 1January 2022 Article No.: 1pp 1–3https://doi.org/10.1145/3475952Online:29 September 2021Publication History 0citation90DownloadsMetricsTotal Citations0Total Downloads90Last 12 Months90Last 6 weeks12 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Physics-informed neural networks (PINNs) is an emerging category of neural networks which can be trained to solve supervised learning tasks while taking into consideration given laws of physics described by general nonlinear partial differential equations. PINNs demonstrate promising characteristics such as performance and accuracy using minimal amount of data for training, utilized to accurately represent the physical properties of a system's dynamic environment. In this work, we employ the emerging paradigm of PINNs to demonstrate their potential in enhancing the security of intelligent cyberphysical systems. In particular, we present a proof-of-concept scenario using the use case of water distribution networks, which involves an attack on a controller in charge of regulating a liquid pump through liquid flow sensor measurements. PINNs are used to mitigate the effects of the attack while demonstrating the applicability and challenges of the approach.

Nowadays notable computing is shifted away from the cloud and performed onto the Internet of Things (IoT) devices. This necessity emerges due to the growing needs not only for real-time decision support but also for real-time data processing. When used in critical applications such as search and rescue missions or monitoring and control of critical infrastructure, the overall reliable operation of the application running on these devices becomes a major challenge, especially as system reliability is an application - and h/w - dependent measure. Moreover, performance and energy are typically constrained and vary depending on where the computation takes place, as well as, on the communication channels between the devices. Hence, the problem of task allocation under reliability performance-energy constraints becomes even more complex in such cloud/hub/edge computing paradigms. In this work, we use a mathematical programming based framework to derive an optimal task allocation based on multiple operational constraints (latency and energy in both computation and communication), while taking into consideration the reliability demands of the application. We consider an architecture consisting of an edge node, an intermediate node (hub), and the cloud infrastructure, and evaluate our approach using a real-life use-case where the proposed framework minimizes the overall latency of the application while considering the reliability demands of each executed task.

This paper is dedicated to the IEEE European Test Symposium (ETS). It offers an overview of all the European Test Workshop and Symposium events, from its first edition in 1996 to the next edition in 2020.

The ability to update firmware in embedded systems allows end-users to patch device vulnerabilities and improve functionality. However, this process is often exploited by adversaries in order to inject malicious firmware code into embedded devices. In this paper, we present a framework which enables highly secure and fast firmware update delivery with minimal downtime on embedded devices. The proposed framework utilizes device intrinsic physical characteristics to authenticate firmware packages along with integrated cryptographic modules to ensure the firmware confidentiality and integrity. A proof-of-concept design is implemented on FPGA, which demonstrates high performance with reasonable overheads, while our analysis shows strong security guarantees.

Current and future multicore architectures can significantly accelerate the performance of test automation procedures depending on the underlying architecture and the scalability of their algorithms. This paper proposes a new parallel methodology targeting the fault simulation problem, for shared memory multicore systems, that maintains scalability with the increase of the number of cores. The method is based on a simple single thread process that allows focusing on the optimization of the parallelization process in different dimensions. Additionally, a number of optimizations are incorporated in the approach to control fault dropping and to avoid unnecessary work. The reported experimental results, for both random and deterministic test sets, demonstrate the scalability of the method. As the number of cores increases, the reported speed-up increases proportionally, where comparable recent methods report saturation or even reduction of the obtained speed-up.

On behalf of the Program, Organizing, and Steering Committees, we would like to extend a warm welcome to everyone attending the European Test Symposium 2017 (ETS'17). ETS has been established as one of the main international forums and the larger forum in Europe that brings together the test community to discuss emerging ideas, views, and trends in the area of electronic-based circuits and system testing. Topics of interest include, but are not limited to, design-for-test, dependability, security, failure analysis and diagnosis, on-line test, automated test hardware, validation and verification, fault simulation, fault tolerance, automatic test generation, etc.

Negative Bias Temperature Instability (NBTI) is a prominent physical failure mechanism which severely degrades the performance of PMOS transistors whenever the voltage at the gate is negatively biased. It leads to catastrophic timing violations in critical circuits and a severe shortening of the overall operational lifetime of the entire system. To alleviate such damaging effects due to NBTI, we present PRITEXT, a novel technique which generates a minimal set of deterministic exercise vectors based on test generation techniques which inherently near-optimizes the bit patterns across each of the generated vectors; the end target being to exercise the critical paths of a device when dormant so as to achieve near-ideal NBTI stress reduction. We explore the design-space of our generated vectors and apply them to our test processor platform under differing sequences, where our evaluation under realistic benchmarks shows that PRITEXT leads to an average 4.99× and a maximum of 13.91× lifetime improvement using 9 generated vectors. In an attempt to reduce hardware overheads even further, we next propose a heuristic to further reduce the number of exercise vectors with minimum loss in lifetime improvement.

A new test generation methodology is proposed that takes advantage of shared memory multi-core systems. Appropriate parallelization of the main steps of ATPG allocates resources in order to minimize workload duplication and multi-threading race contention, often encountered in parallel implementations. The proposed approach ensures that the obtained acceleration grows linearly with the number of processing cores and, at the same time, keeps the test set size close to that obtained by serial ATPG. The experimental results demonstrate that the proposed methodology achieves higher degree of speed-up than comparable state-of-the-art multi-core based tools, while maintains similar test set sizes.

On behalf of the Steering, Program and Organizing Committees, we would like to welcome you to the European Test Symposium 2016 (ETS'16); the largest event in Europe entirely devoted to presenting and discussing scientific trends, emerging results, hot topics, and applications in the area of electronic circuit and system testing. ETS'16 is the 21st edition of the symposium and is held in Amsterdam, The Netherlands. Amsterdam is the capital and most populous city of the Kingdom of the Netherlands. Amsterdam's name derives from Amstelredamme, indicative of the city's origin as a dam of the river Amstel.

Multicore architectures can significantly accelerate the performance of well-established design and test automation processes, provided that the underlying process is scalable with respect to the system on which it is executed. In this work we concentrate on fault simulation and propose a new parallel process for shared-memory multicore systems, capable of maintaining its scalability as the number of processing cores utilized increases. In order to maximize parallelization, the method utilizes a simple, non-optimized single thread simulation process, which allows for high degrees of freedom to be exploited by three different and combined dimensions of parallelism. Simulation data is distributed to the available cores in a balanced fashion in order to favor speed-up over single-core executions and, ultimately, scalability. The experimental results show that the proposed approach achieves high speed-up rates which, in contrast to comparable state-of the-art methods, increase monotonically with the number of cores demonstrating a highly scalable solution.

As technology scales deep into the sub-micron regime, transistors become less reliable. Future systems are widely predicted to suffer from considerable aging and wear-out effects. This ominous threat has urged system designers to develop effective run-time testing methodologies that can monitor and assess the system's health. In this work, we investigate the potential of online software-based functional testing at the granularity of individual microprocessor core components in multi-/many-core systems. While existing techniques monolithically test the entire core, our approach aims to reduce testing time by avoiding the over-testing of under-utilized units. To facilitate fine-grained testing, we introduce DaemonGuard, a framework that enables the real-time observation of individual sub-core modules and performs on-demand selective testing of only the modules that have recently been stressed. Moreover, we investigate the impact of the cache hierarchy on the testing process and we develop a cache-aware selective testing methodology that significantly expedites the execution of memory-intensive test programs. The monitoring and test-initiation process is orchestrated by a transparent, minimally-intrusive, and lightweight operating system process that observes the utilization of individual datapath components at run-time. We perform a series of experiments using a full-system, execution-driven simulation framework running a commodity operating system, real multi-threaded workloads, and test programs. Our results indicate that operating-system-assisted selective testing at the sub-core level leads to substantial savings in testing time and very low impact on system performance. Additionally, the cache-aware testing technique is shown to be very effective in exploiting the memory hierarchy to further minimize the testing time.

The high accuracy of the Path Delay Fault model (PDF) is usually sidelined by its high complexity since the number of possible faults can become exponential to the circuit size (even when only critical faults are considered). Thus, fault simulation may require prohibitively large memory resources. In this work we propose a test reordering technique to control the complexity of exact PDF grading when Zero-suppressed Binary Decision Diagrams are used for fault representation. Experimentation on path dense benchmark circuits demonstrates considerable reduction in memory requirements for the PDF grading problem.

In this paper, we propose an FPGA-based emulation framework that can provide dynamic vulnerability analysis for hardware-accelerated computer vision applications. The framework can be integrated alongside the targeted application, to allow for run-time, in-field, dynamically adjusted vulnerability analysis in real-world conditions, taking into consideration the non-deterministic parameters of the computer vision algorithm computations. We evaluate the proposed framework in real-time using an FPGA platform, for an obstacle avoidance (OA) computer vision application and its disparity estimation kernel to study the impact of Single-Event Upsets (SEUs).

In-field on-line testing techniques have recently been proposed for permanent fault detection caused by wear-out/aging-related defects manifesting during the lifetime of a system. Selective Software-Based Self-Testing (SBST) is one such paradigm focusing primarily on the recently stressed functional units of a multicore system at a sub-core granularity, in an attempt to reduce the application performance penalty caused by periodically testing the entire system. In this work, we complement our O/S-enabled framework DeamonGuard for on-demand (selective) SBST to support fault recovery capabilities. Towards this goal, we propose an efficient check pointing and rollback recovery mechanism which, upon fault detection, can restore the system to the most recently valid correct state and resume the normal operation assuming disabling of the faulty core, thereby leading to a healthy (but degraded) system. The work in this paper concentrates on reducing the number of stored checkpoints required when testing at a sub-core granularity, and minimizing the recovery penalty of such framework. We evaluate and demonstrate the overhead of the proposed recovery mechanism, and our results indicate a practical reduction in the number of stored checkpoints as well as a significant improvement in recovery latency for the cases where the faults are correlated with the stressed units.

The notion of Architectural Vulnerability Factor (AVF) has been extensively used to evaluate various aspects of design robustness. While AVF has been a very popular way of assessing element resiliency, its calculation requires rigorous and extremely time-consuming experiments. Furthermore, recent radiation studies in 90 nm and 65 nm technology nodes demonstrate that up to 55 percent of Single Event Upsets (SEUs) result in Multiple Bit Upsets (MBUs), and thus the Single Bit Flip (SBF) model employed in computing AVF needs to be reassessed. In this paper, we present a method for calculating the vulnerability of modern microprocessors -using Statistical Fault Injection (SFI)- several orders of magnitude faster than traditional SFI techniques, while also using more realistic fault models which reflect the existence of MBUs. Our method partitions the design into various hierarchical levels and systematically performs incremental fault injections to generate vulnerability estimates. The presented method has been applied on an Intel microprocessor and an Alpha 21264 design, accelerating fault injection by 15×, on average, and reducing computational cost for investigating the effect of MBUs. Extensive experiments, focusing on the effect of MBUs in modern microprocessors, corroborate that the SBF model employed by current vulnerability estimation tools is not sufficient to accurately capture the increasing effect of MBUs in contemporary processes.

Moore's Law scaling continues to yield higher transistor density with each succeeding process generation, leading to today's many-core chip multiprocessors (CMPs) with tens or even hundreds of interconnected cores or tiles. Unfortunately, deep submicron CMOS process technology is marred by increasing susceptibility to wear. Prolonged operational stress gives rise to accelerated wearout and failure due to several physical failure mechanisms, including hot-carrier injection (HCI) and negative-bias temperature instability (NBTI). Each failure mechanism correlates with different usage-based stresses, all of which can eventually generate permanent faults. While the wearout of an individual core in many-core CMPs may not necessarily be catastrophic, a single fault in the interprocessor network-on-chip (NoC) fabric could render the entire chip useless, as it could lead to protocol-level deadlocks, or even partition away vital components such as the memory controller or other critical I/O. In this article, we study HCI- and NBTI-induced wear due to actual stresses caused by real workloads, applied onto the interconnect microarchitecture and develop a critical path model for NBTI-induced wearout. A key finding of this modeling is that, counter to prevailing wisdom, wearout in the CMP's on-chip interconnect is correlated with lack of load observed in the NoC routers rather than high load. We then develop a novel wearout-decelerating scheme in which routers under low load have their wear-sensitive components exercised without significantly impacting cycle time, pipeline depth, area, or power consumption of the overall router. A novel deterministic approach is proposed for the generation of appropriate exercise-mode data, ensuring design parameter targets are met. We subsequently show that the proposed design yields an ∼2,300× decrease in the rate of wear.

We propose a technology-independent vulnerability-driven parity selection method for protecting modern microprocessor in-core memory arrays against multiple-bit upsets (MBUs). As MBUs constitute over 50% of the upsets in recent technologies, error correcting codes or physical interleaving are typically employed to effectively protect out-of-core memory structures, such as caches. Such methods, however, are not applicable to high performance in-core arrays, due to computational complexity, high delay, and area overhead. Therefore, we investigate vulnerability-based parity forest formation as an effective mechanism for detecting errors. Checkpointing and pipeline flushing can subsequently be used for correction. As the optimal parity tree construction for MBU detection is a computationally complex problem, an integer linear program formulation is introduced. In addition, vulnerability-based interleaving (VBI) is explored as a mechanism for further enhancing in-core array resiliency in constrained, single parity tree cases. VBI first physically disperses bitlines based on their vulnerability factor and then applies selective parity to these lines. Experimental results on Alpha 21264 and Intel P6 in-core memory arrays demonstrate that the proposed parity tree selection and VBI methods can achieve vulnerability reduction up to 86%, even when a small number of bits are added to the parity trees.

This work proposes a reverse topological ordering for the variables of Zero-suppressed Binary Decision Diagrams (ZBDD) which bounds their size when used to represent the paths of a Directed Acyclic Graph (DAG). Specifically, the size of a ZBDD representing all paths of a DAG is shown to be linear to the number of the edges in the DAG.

We propose an AVF-driven parity selection method for protecting modern microprocessor in-core memory arrays against MBUs. As MBUs constitute more than 50% of the upsets in latest technologies, error correcting codes or physical interleaving are typically employed to effectively protect out-of-core memory structures, such as caches. However, such methods are not applicable to high-performance in-core arrays, due to computational complexity, high delay and area overhead. To this end, we revisit parity as an effective mechanism to detect errors and we resort to pipeline flushing and checkpointing for correction. We demonstrate that optimal parity tree construction for MBU detection is a computationally complex problem, which we then formulate as an integer-linear-program (ILP). Experimental results on Alpha 21264 and Intel P6 in-core memory arrays demonstrate that optimal parity tree selection can achieve great vulnerability reduction, even when a small number of bits are added to the parity trees, compared to simple heuristics. Furthermore, the ILP formulation allows us to find better solutions by effectively exploring the solution space in the presence of multiple parity trees; results show that the presence of 2 parity trees offers a vulnerability reduction of more than 50% over a single parity tree.

We investigate the complexity and utility of performing Multiple Bit Upset (MBU) vulnerability analysis in modern microprocessors. While the Single Bit Flip (SBF) model constitutes the prevailing mechanism for capturing the effect of Single Event Upsets (SEUs) due to alpha particle or neutron strikes in semiconductors, recent radiation studies in 90nm and 65nm technology nodes demonstrate that up to 55% of such strikes result in Multiple Bit Upsets (MBUs). Consequently, the accuracy of popular vulnerability analysis methods, such as the Architecural Vulnerability Factor (AVF) and Failures In Time (FIT) rate estimates based on the SBF assumption comes into question, especially in modern microprocessors which contain a significant amount of memory elements. Towards alleviating this concern, we present an extensive infrastructure which enables MBU vulnerability analysis in modern microprocessors. Using this infrastructure and a modern microprocessor model, we perform a large scale MBU vulnerability analysis study and we report two key findings: (i) the SBF fault model overestimates vulnerability by up to 71%, as compared to a more realistic modeling and distribution of faults in the 90nm and 65nm processes, and (ii) the rank-ordered lists of critical bits, as computed through the SBF and MBU models, respectively, are very similar, as indicated by the average rank difference of a bit which is less than 1.45%.

We present a novel methodology for protecting incore microprocessor memory arrays from Multiple Bit Upsets (MBUs). Recent radiation studies in modern SRAMs demonstrate that up to 55% of Single Event Upsets (SEUs) due to alpha particle or neutron strikes result in MBUs. Towards suppressing these MBUs, methods such as physical interleaving or periodic scrubbing have been successfully applied to caches. However, these methods are not applicable to in-core, high-performance Content-Addressable Memories (CAM) arrays, due to computational complexity, high delay and area overhead, and lack of information redundancy. To this end, we propose a cost-effective method for enhancing in-core memory array resiliency, called Vulnerability-based Interleaving (VBI). VBI physically disperses bit-lines based on their vulnerability factor and applies selective parity to these lines. Thereby, VBI aims to ensure that an MBU will affect at most one critical bit-field, so that the selective parity will detect the error and a subsequent pipeline flush will remove its effects. Experimental results employing simulation of realistic MBU fault models on the instruction queue of the Alpha 21264 microprocessor in a 65nm process, demonstrate that a 30% selective parity protection of VBI-arranged bit-lines reduces vulnerability by 94%.

While defect oriented testing in digital circuits is a hard process, detecting a modeled fault more than one time has been shown to result in high defect coverage. Previous work shows that such test sets, known as multiple detect orn-detect test sets, are of increased quality for a number of common defects in deep sub-micrometer technologies. Method for multiple detect test generation usually produce fully specified test patterns. This limits their usage in a number of important applications such as low power test and test compression. This work proposes a systematic methodology for identifying a large number of bits that can be unspecified in a multiple detect (n-detect) test set, while preserving the original fault coverage. The experimental results demonstrate that the number of specified bits in, even compact,n-detect test sets can be significantly reduced without any impact on then-detect property. Additionally, in many cases, the size of the test set is reduced.

The correlation between the physical paths of a digital circuit has important implications in various design automation problems, such as timing analysis, test generation and diagnosis. When considering the complexity and tight timing constraints of modern circuits, this correlation affects both the design process and the testing approaches followed in manufacturing. In this work we quantify the diversity of a set of paths (or path segments), let these be critical I/O paths, error propagation paths for various fault models, or paths traced for diagnostic purposes. Circuit paths are encoded using Zero-Suppressed Binary Decision Diagrams (ZBDDs), the proposed method consists of a sequence of standard ZBDD operations to provide a measure of the overlap of the paths under consideration. The main contribution of the presented method is that, path or path segment enumeration is entirely avoided and, hence, a large number of paths can be considered in practical time. Experimentation using standard benchmark circuits demonstrates the effectiveness of the approach in showing the difference in path correlation between various critical I/O path sets.

Reliability of CMOS devices emerges as a vital design constraint, evidenced by several CMOS failure mechanisms. Such mechanisms have traditionally been modeled independently, using statistical approximation techniques to estimate Mean-Time-to-Failure (MTTF) rates. This paper proposes a unified framework that integrates the existing failure models into a multi-objective optimization engine, in an attempt to provide a pareto-optimal solution indicating the suggested operating conditions of a system for a given technology and size (in transistors), in an effort to maximize its lifetime reliability. In addition to the existing failure mechanisms, the framework also considers a proposed system-level leakage power estimation model, as leakage is interdependent on temperature, and as such impacts system reliability. The framework can be used in several design scenarios, such as thermal-aware task scheduling.

QAM is a widely used multi-level modulation technique, with a variety of applications in data radio communication systems. Most existing implementations of QAM-based systems use high levels of modulation in order to meet the high data rate constraint of emerging applications. This work presents the architecture of a highly-parallel MPSoC-based QAM modulator that offers multi-rate modulation. The proposed MPSoC architecture is modular and provides flexibility via dynamic reconfiguration of the QAM, offering high data rates (more than 1 Gbps), even at low modulation levels (16-QAM). Furthermore, the proposed QAM implementation integrates a hardware-based resource allocation algorithm for dynamic load balancing.

It has been previously shown that in order to guarantee the temporal correctness of a circuit, only the primitive path delay fault set needs to be tested. However, as in the case of the traditional and simpler path delay fault model, the number of possible faults can be exponential to the circuit size and, therefore, it is only practical to consider the set of critical faults. This work defines critical primitive path delay faults and presents an exact algorithm to identify them, using zero-suppressed binary decision diagrams and newly introduced operators necessary for handling multiple path delay faults. We report the number of critical primitive path delay faults for various criticality thresholds under the bounded delay model. The results indicate that only a small, but still necessary, number of multiple (primitive) faults, which escape testing under the singly testable fault criterion, must be considered in order to guarantee the timing correctness of the circuit.

This work presents two new methods for the generation of test sets with a small number of specified bits. Such type of test sets have been proven beneficial to a large number of test-related applications such as deterministic BIST, low power testing and test set enrichment. The first technique is static, since it considers an initial test set which attempts to relax via test replacement with tests of similar coverage but with fewer specified bits. The second technique is dynamic; it generates a test set from a zero base using a hierarchical fault-compatibility algorithm. Both methods are applicable to any enumerative fault method (linear to the circuit size). The experiments performed using the stuck-at fault model demonstrate the superiority of the proposed methods over comparable existing techniques, in reducing the total number of specified bits per generated test set. The applicability of the generated relaxed test sets is demonstrated for one, out of the many, possible applications, that of deterministic test set embedding. A general framework that integrates the proposed relaxation methods in two popular LFSR-based test set embedding schemes (full and partial reseeding), along with a systematic exploration of related parameters, is proposed. The obtained results show significant reductions in seed storage requirements.

Next generation multiprocessor systems-on-chip (MPSoCs) are expected to contain numerous processing elements, interconnected via on-chip networks, executing real-time applications. It is anticipated that runtime optimization algorithms which dynamically adjust system parameters with the purpose of optimizing the system's operation, will be embedded in the system software and/or hardware. In this paper, we present a methodology for simulating and evaluating system-level optimization algorithms, demonstrated by the case of on-chip dynamic task allocation applied to generic MPSoC architectures. Through this methodology, we are able to show that dynamic, system-level bidding-based task allocation can improve system performance, when compared to a round robin allocation, in popular MPSoC applications.

This paper presents an innovative approach for the generation of functional programs to test path- delay faults within microprocessors. The proposed method takes advantage of both the gate- and RT-level description of the processor. The former is used to build binary decision diagrams (BDDs) for deriving fault excitation conditions; the latter is exploited for the automatic generation of test programs able to excite and propagate fault effects, based on an evolutionary algorithm and fast RTL simulation. Experimental results on a simple microcontroller show that the proposed methodology is able to generate suitable test sets in reduced times.

While defect oriented testing in digital circuits is a hard process, detecting a modeled fault more than one time has been shown to result in high defect coverage. Previous work shows that such test sets, known as n-detect test sets, are of increased quality for a number of common defects in deep sub-micron technologies, n-detect test generation methods usually produce fully specified test patterns. This limits their usage in a number of important applications such as low power test and test compression. This work proposes a systematic methodology for identifying a large number of bits that can be unspecified in an n-detect test set, while preserving the n-detection property, in contrast to any other existing test set relaxation method. The experimental results demonstrate that the number of specified bits in, even compact, n- detect test sets can be significantly reduced without any impact on the n-detect property.

A new way of fault collapsing for effect-cause diagnosis is presented. In contrast to existing dominance-based methods which operate on a pair of faults, the proposed method operates on pairs of sets of faults. The impact of the proposed method is evaluated with respect to effect-cause diagnosis. Experimental results show that the proposed collapsing methods can reduce the diagnostic simulation time on an average of 31% when compared to the existing techniques

We propose a novel method for generating test patterns that can be encoded efficiently using reseeding of LFSR-based schemes for hybrid BIST. Our focus is to reduce the number of deterministic tests while keeping their overall number of specified bits small and, thus, reduce the storage requirements for the LFSR seeds. The proposed solution is based on test function manipulation and generates a compact test set in which individual tests have a high number of unspecified bits. The method uses binary decision diagrams (BDDs) and a modified version of the min-cost max-matching problem on graphs. The obtained experimental results clearly demonstrate the impact of the proposed ATPG algorithm in reducing the on-chip seed storage, when combined with the considered BIST schemes

This paper presents a new way of fault collapsing called dominance with sub-faults(DSF) collapsing. The proposed approach reduces the number of tests required to diagnose a fault. Experimental results on the ISCAS'85 benchmarks demonstrate the impact of the proposed method over the traditional fault collapsing method

A method to implicitly derive all tests for each transition fault under established fault-sensitization criteria is presented. The derived quality test functions are enhanced in three different ways to derive better quality test sets. One enhancement restricts fault sensitization along critical subcircuits whose paths have long delays under a fixed-delay model. Another manipulates the functions to generate compact test sets. The last one enriches the test set with additional test vectors so that transition faults are tested through several activation and propagation paths without path enumeration. Experimental results demonstrate the effectiveness of deriving such enhanced test functions

A recent method generates high quality tests for transition faults using functions. Event sensitization criteria as well as path lengths can be taken into consideration during the generation of such test functions. It is shown how to manipulate the test functions to generate compact test sets. Experimental results on ISCAS'85 and ISCAS'89 circuits show that a compaction rate of the order of 70% to 84% is achieved without compromising fault coverage. Moreover, a novel method to enrich the compacted test set with additional vectors is presented so that transition faults are tested through different activation and propagation paths. Such test sets havehigher quality, compared to traditional transition fault test sets, since events propagate through many critical paths.

A function representing path delay faults (PDFs) together with their nonrobust test cubes is presented. The function is manipulated effectively using zero suppressed binary decision diagrams (ZBDDs) and irredundant sum of products (ISOPs) in ZBDD-based representation, and is derived using a polynomial number, to the circuit size, of standard ZBDD operations. This new data structure can be used effectively during the ATPG process to derive high quality test sets. Experimental results demonstrate that the proposed structure can be implemented efficiently.

We present a function-based nonenumerative automatic test pattern generation (ATPG) methodology for detecting path delay faults (PDFs). The proposed technique consists of a number of topological circuit traversals during each a linear number of Boolean functions is generated per circuit line. From each such function we derive a test that detects many PDFs. The two major strengths of the approach, that stem from the function-based formulations used, are very compact test sets, and scalability in test efficiency. The performance of an implementation based on binary decision diagrams is evaluated and compared with existing compact methods to demonstrate the superiority of the proposed method.

We present a generic framework that supports efficient generation of the traditional Boolean difference function of some output with respect to any line in a combinational circuit, which is important when testing for logic defects. The framework also allows for the generation of generalized Boolean difference functions, which reflect sensitivity on event propagation from a given line to some circuit output. This generalized function could apply in timing verification, analysis, and test. We implemented the proposed framework using various function representation environments, including binary decision diagrams, Boolean expression diagrams, and Boolean networks, and report experimental results on the ISCAS'85 and ISCAS'89 benchmarks.

We formulate the path delay fault (PDF) coverage problem as a combinatorial problem that amounts to storing and manipulating sets using a special type of binary decision diagrams, called zero-suppressed binary decision diagrams (ZBDD). The ZBDD is a canonical data structure inherently having the property of representing combinational sets very compactly. A simple modification of the proposed basic scheme allows us to increase significantly the storage capability of the data structure with minimal loss in the fault coverage accuracy. Experimental results on the ISCAS85 benchmarks show considerable improvement over all existing techniques for exact PDF grading. The proposed methodology is simple, it consists of a polynomial number of increasingly efficient ZBDD-based operations, and can handle very large test sets that grade very large number of faults.

We present an ATPG tool for functional delay faults which applies to the single-input transition (SIT) and the multi-input transition (MIT) fault models, and is based on Reduced Ordered Binary Decision Diagrams (ROBDDs). We are able, for the first time, to identify all faults that do not have any SIT tests, and generate all SIT tests for nonredundant faults in combinational circuits. We also provide methodologies for efficient generation of MIT tests. Our experimental results on the ISCAS'85 benchmarks is by far superior to existing methods as well as a Satisfiability-based tool that we have developed for comparative purposes. The presented tool, coupled with advancements in path delay fault coverage, shows that both the SIT and MIT functional models are very useful in ATPG for robust path delay faults for synthesized circuits.

Formulates the fault grading problem as a combinatorial problem that amounts to storing and manipulating sets on a special type of binary decision diagrams (BDDs), called zero-suppressed BDDs (ZBDDs), that represent sets in a unique and compact manner. A simple modification of the basic scheme allows us to overcome memory problems that may arise by complex set representation. Experimental results on the ISCAS'85 benchmarks show considerable improvement over all existing techniques for exact PDF grading. The main advantages of the proposed methodology are the simplicity of the approach, in terms of it being expressed by a polynomial number of increasingly efficient BDD-based operations, its organization, and its ability to handle very large test sets.

This paper presents a functional level ATPG tool for delay faults which handles all existing fault models. The tool generates patterns using either binary decision diagrams or Boolean satisfiability. Experimental results are presented on the ISCAS'85 benchmarks.