EDBT 2026 Demo / reviewers in the wild / expert
Wei Xi 0001
dblp:10/264-1
· DBLP profile ↗
4ranked-venue papers
0as first author
4since 2021 · last 2026
0000-0002-9061-7754ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 3 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Adaptive All-Digital Clock Data Calibration Circuit for Chiplet Interfaces
Zhenming Li, Pengkang Luo, Guowei Xing, Xiaowen Jiang 0001, Wei Xi 0001, Kai Huang 0002 |
ISCAS | 5 |
| 2026 | An Efficient BIST and Fault Diagnosis Circuit for TSVs
Guowei Xing, Xiaowen Jiang 0001, Pengkang Luo, Zhenming Li, Wei Xi 0001, Kai Huang 0002 |
ISCAS | 5 |
| 2023 | Structured Term Pruning for Computational Efficient Neural Networks InferenceabstractThe state-of-the-art convolutional neural network accelerators are showing a growing interest in exploiting the bit-level sparsity and eliminating the ineffectual computations of zero bits. However, the excessive redundancy and the irregular distribution of nonzero bits limit the real speedup in the accelerators. To address this, we propose an algorithm-architecture codesign, named structured term pruning (STP), to boost the computation efficiency of neural networks inference. Specifically, we enhance the bit sparsity by guiding the weights toward the value with fewer power-of-two terms. Then, we structure the terms with layer-wise group budgets. Retraining is adopted to recover the accuracy drop. We also design the hardware of the group processing element and the fast signed-digital encoder for efficient implementation of STP networks. The system design of STP is realized with some easy alterations on an input stationary systolic array design. Extensive evaluation results demonstrate that STP can reduce significant inference computation costs, and achieve$2.35\times $computational energy saving for the ResNet18 network on the ImageNet dataset. Kai Huang 0002, Bowen Li 0017, Siang Chen, Luc Claesen, Wei Xi 0001, Junjian Chen, Xiaowen Jiang 0001, Zhili Liu, Dongliang Xiong, Xiaolang Yan |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 5 |
| 2023 | Cloud-Edge Collaboration-Based Local Voltage Control for DGs With Privacy PreservationabstractThe increased distributed generators (DGs) have exacerbated voltage violations in active distribution networks (ADNs). Local reactive power control of DG inverters can realize a fast response to frequent voltage fluctuations. However, commonly used model-based voltage control depends upon accurate network parameters and entire ADN data, which may cause the sensitive information leakage of ADN and DG behaviors in practical operation. In this article, a cloud-edge collaboration-based local voltage control strategy for DGs is proposed with privacy preservation. First, a local voltage control framework is established based on cloud-edge collaboration, in which a surrogate model is built based on the graph convolutional neural networks to estimate the ADN voltages. By transferring the surrogate model, the edge side can obtain the exact voltage estimation in the local curve tuning process without the authority of the whole ADN data, preserving the network parameters of ADN. Then, the interarea coordination based on federated learning is proposed to realize the parameter updating of DG control curves, which can achieve better voltage control performance. By updating surrogate submodels based on private data distributed across multiple edge devices, federated learning can effectively preserve DG behaviors. Finally, the effectiveness and adaptability of the proposed control strategy are validated using the modified IEEE 33-node system. The proposed local DG control strategy can effectively cope with voltage problems and enhance the adaptability to variations in practical operation states while considering privacy preservation. Jinli Zhao, Hao Yu 0025, Haoran Ji, Peng Li 0014, Wei Xi 0001, Jinyue Yan, Chengshan Wang |
IEEE Trans. Ind. Informatics | 6 |