The evolution of sixth-generation (6G) wireless communication significantly accelerates the Internet of vehicles innovation, catalyzing advancements in autonomous driving systems. The collaborative model utilizing 6G is expected to break through the vehicle’s inherent field-of-view deficiencies and heterogeneous computational resource constraints, further improving the efficiency of the technology. This paper proposes a novel 6G NOMA air-ground integrated sensing-computing framework that achieves high-quality collaborative perception and low-latency 3D computing offloading to alleviate restrictions through cooperative networking with unmanned aerial vehicles (UAVs) and road-side units (RSUs). To balance latency and UAV energy consumption for efficient collaboration, we formulate it as a mixed integer nonlinear programming problem (MINLP). Considering the time sensitivity of the perceptual task, we introduce queuing and Lyapunov optimization theory to transform the optimization objective into a Lyapunov drift-penalty function and derive its upper bound, which we model as a Markov decision process (MDP) and optimize it with Large Language Models (LLMs) assisted temporal replay deep reinforcement learning (TR-DRL). For perception quality improvement, an elite-guided binary-weighted firefly algorithm is developed to solve combinatorial optimization in perception fusion. Experimental results demonstrate 4.88% and 8.26% improvements in latency and energy efficiency respectively, alongside enhanced perception fusion quality 7.41% compared with advanced counterparts.

In vehicular edge computing (VEC) networks, by implementing content caching and V2X connectivity, road side unit (RSU) and nearby vehicles can serve as platforms for rapid data retrieval to address mobile traffic explosion. However, due to the dynamic and multi-constrained environment consisting of heterogeneous vehicles and RSU, it is challenging to meticulously plan cooperative caching policies. Additionally, due to the diversity of contents and the mobility of vehicles, the caching policy space is massive, which can be fatal for vehicles with limited computing and energy. In this paper, we formulate cooperative content caching in VEC networks as Markov decision process (MDP), configuring caching policies for vehicles and RSU. Our aim is to minimize Lyapunov drift and long-term delay. To address the massive caching policies, we propose a two-stage deep reinforcement learning (TS-DRL) algorithm. In the first stage, an improved ant colony algorithm is used to generate unilateral suggestions and construct action space to avoid the curse of dimensionality. In the second stage, we combine the Noisy Net and Double Deep Q-Learning Network to avoid overestimating value and efficient exploration problem. Simulation results show that TS-DRL outperforms advanced algorithms in terms of delay and cache hit rate.

By allowing timing errors to occur and recovering them online, resilient systems can be used to eliminate the voltage/frequency guardband to improve energy efficiency/throughput. Due to the nature of fault tolerance computing, resilient systems have a different binning strategy from traditional circuits. In this paper, we study, for the first time, the binning metrics of resilient systems. We propose a solution for resilient system binning based on structural at-speed delay testing. Then an adaptive clock configuration technique is proposed for yield improvement. Experimental results demonstrate the effectiveness of our proposed binning method, and significant yield improvement accomplished by the adaptive clock configuration technique.

This paper presents a new at-speed logic built-in self-test (BIST) architecture supporting two launch-on-capture schemes, namely aligned double-capture and staggered double-capture, for testing multi-frequency synchronous and asynchronous clock domains in a scan-based BIST design. The proposed architecture also includes BIST debug and diagnosis circuitry to help locate BIST failures. The aligned scheme detects and allows diagnosis of structural and delay faults among all synchronous clock domains, whereas the staggered scheme detects and allows diagnosis of structural and delay faults among all asynchronous clock domains. Both schemes solve the long-standing problem of using the conventional one-hot scheme, which requires testing each clock domain one at a time, or the simultaneous scheme, which requires adding isolation logic to normal functional paths across interacting clock domains. Physical implementation is easily achieved by the proposed solution due to the use of a slow-speed, global scan enable signal and reduced timing-critical design requirements. Application results for industrial designs demonstrate the effectiveness of the proposed architecture.

This paper describes a core-based test and diagnosis integration and automation system, called Turbo1500, which automatically synthesizes test and diagnosis logic in accordance with the IEEE 1500 standard. Turbo1500 serves two major purposes. One is for use as a core test automation tool in a system-on-chip (SOC) environment to automatically connect multiple cores from various sources and create testbenches each targeting an individual core under the control of a chip-level test access port (TAP) controller. The other is for hierarchical (block-by-block) core test and diagnosis when chips on a printed-circuit board are embedded with 1149.1 boundary scan I/O cells and cores under test and diagnosis are surrounded with 1500-compliant wrapper cells. Application experience showed that the simplicity of the IEEE 1500 standard combined with an easy-to-use automation tool can make core-based design for test and diagnosis no longer a nightmare, especially when some cores are extremely large or complex.