During these days of global emergency for the COVID-19 disease outbreak, there is an urgency to share reliable information able to help worldwide life scientists to get better insights and make sense of the large amount of data currently available. In this study we used the results presented in [1] to perform two different Systems Biology analyses on the HCoV-host interactome. In the first one, we reconstructed the interactome of the HCoV-host proteins, integrating it with highly reliable miRNA and drug interactions information. We then added the IL-6 gene, identified in recent publications [2] as heavily involved in the COVID-19 progression and, interestingly, we identified several interactions with the reconstructed interactome. In the second analysis, we performed a Gene Ontology and a Pathways enrichment analysis on the full set of the HCoV-host interactome proteins and on the ones belonging to a significantly dense cluster of interacting proteins identified in the first analysis. Results of the two analyses provide a compact but comprehensive glance on some of the current state-of-the-art regulations, GO, and pathways involved in the HCoV-host interactome, and that could support all scientists currently focusing on SARS-CoV-2 research.

The spread of antibiotic resistance is a growing problem known to be caused by antibiotic usage itself. This problem can be analyzed at different levels. Antibiotic administration policies and practices affect the societal system, which is made by human individuals and by their relations. Individuals developing resistance interact with each other and with the environment while receiving antibiotic treatments moving the problem at a different level of analysis. Each individual can be further see as a meta-organism together with his associated microbiotas, which prove to have a prominent role in the resistance spreading dynamics. Eventually, in each microbiota, population dynamics and vertical or horizontal transfer events implement cellular and molecular mechanisms for resistance spreading and possibly for its prevention. Using the Nets-within-nets formalism, in this work we model the relation between different antibiotic administration protocols and resistance spread dynamics both at the human population and at the single microbiota level.

Biological analysis applications are usually high demanding in terms of computational power required. Cloud Computing infrastructures can be of great value supporting those type of applications, thanks to the high flexibility and performing hardware provided. The merging of solutions based on MapReduce and distributed file systems services, allows the creation of scalable infrastructures and data management services adaptable to various use cases and requirements. However, the implementation and deployment of cloud based services remains a complex task for biological researchers without specific skills. In this paper authors describe a service that allows the execution of a biological networks simulation tool in cloud, implemented with the aid of MapReduce algorithms called MaReX. The paper shows in detail the interactions occurring between the various components of the platform such as: database, process manager agent and graphical user interface.

BACKGROUND: Biological research increasingly relies on network models to study complex phenomena. Signal Transduction Pathways are molecular circuits that model how cells receive, process, and respond to information from the environment providing snapshots of the overall cell dynamics. Most of the attempts to reconstruct signal transduction pathways are limited to single regulator networks including only genes/proteins. However, networks involving a single type of regulator and neglecting transcriptional and post-transcriptional regulations mediated by transcription factors and microRNAs, respectively, may not fully reveal the complex regulatory mechanisms of a cell. We observed a lack of computational instruments supporting explorative analysis on this type of three-component signal transduction pathways. RESULTS: We have developed CyTRANSFINDER, a new Cytoscape plugin able to infer three-component signal transduction pathways based on user defined regulatory patterns and including miRNAs, TFs and genes. Since CyTRANSFINDER has been designed to support exploratory analysis, it does not rely on expression data. To show the potential of the plugin we have applied it in a study of two miRNAs that are particularly relevant in human melanoma progression, miR-146a and miR-214. CONCLUSIONS: CyTRANSFINDER supports the reconstruction of small signal transduction pathways among groups of genes. Results obtained from its use in a real case study have been analyzed and validated through both literature data and preliminary wet-lab experiments, showing the potential of this tool when performing exploratory analysis.

Research centers performing biomedical research collide with the problem of the treatment of large amounts of data. Several scientific fields in biomedical adopt technologies that can analyze samples in a more accurate way thanks to the high granularity which the current equipment provide the results. The cloud computing technology allows to create scalable and flexible infrastructures and data management services. In recent years the number of solutions that can be included within the phenomenon of cloud computing has increased. There are many cases of distributed solutions with high storage and processing capacity and the possibility of serving a large number of users. In this paper authors describe a biological networks modeling tool, implemented with the aid of MapReduce algorithms that works on a cluster in a cloud computing infrastructure.

Uncharacterized proteins pose a challenge not just to functional genomics, but also to biology in general. The knowledge of biochemical functions of such proteins is very critical for designing efficient therapeutic techniques. The bottleneck in hypothetical proteins annotation is the difficulty in collecting and aggregating enough biological information about the protein itself. In this paper, we propose and evaluate a protein annotation technique that aggregates different biological information conserved across many hypothetical proteins. To enhance the performance and to increase the prediction accuracy, we incorporate term specific relationships based on Gene Ontology (GO). Our method combines PPI (Protein Protein Interactions) data, protein motifs information, protein sequence similarity and protein homology data, with a context similarity measure based on Gene Ontology, to accurately infer functional information for unannotated proteins. We apply our method on Saccharomyces Cerevisiae species proteins. The aggregation of different sources of evidence with GO relationships increases the precision and accuracy of prediction compared to other methods reported in literature. We predicted with a precision and accuracy of 100% for more than half proteins of the input set and with an overall 81.35% precision and 80.04% accuracy.

What is the probability that the execution state of a given microprocessor running a given application is correct, in a certain working environment with a given soft-error rate? Trying to answer this question using fault injection can be very expensive and time consuming. This paper proposes the baseline for a new methodology, based on microprocessor error probability profiling, that aims at estimating fault injection results without the need of a typical fault injection setup. The proposed methodology is based on two main ideas: a one-time fault-injection analysis of the microprocessor architecture to characterize the probability of successful execution of each of its instructions in presence of a soft-error, and a static and very fast analysis of the control and data flow of the target software application to compute its probability of success. The presented work goes beyond the dependability evaluation problem; it also has the potential to become the backbone for new tools able to help engineers to choose the best hardware and software architecture to structurally maximize the probability of a correct execution of the target software.

BACKGROUND: The collection of gene expression profiles from DNA microarrays and their analysis with pattern recognition algorithms is a powerful technology applied to several biological problems. Common pattern recognition systems classify samples assigning them to a set of known classes. However, in a clinical diagnostics setup, novel and unknown classes (new pathologies) may appear and one must be able to reject those samples that do not fit the trained model. The problem of implementing a rejection option in a multi-class classifier has not been widely addressed in the statistical literature. Gene expression profiles represent a critical case study since they suffer from the curse of dimensionality problem that negatively reflects on the reliability of both traditional rejection models and also more recent approaches such as one-class classifiers. RESULTS: This paper presents a set of empirical decision rules that can be used to implement a rejection option in a set of multi-class classifiers widely used for the analysis of gene expression profiles. In particular, we focus on the classifiers implemented in the R Language and Environment for Statistical Computing (R for short in the remaining of this paper). The main contribution of the proposed rules is their simplicity, which enables an easy integration with available data analysis environments. Since in the definition of a rejection model tuning of the involved parameters is often a complex and delicate task, in this paper we exploit an evolutionary strategy to automate this process. This allows the final user to maximize the rejection accuracy with minimum manual intervention. CONCLUSIONS: This paper shows how the use of simple decision rules can be used to help the use of complex machine learning algorithms in real experimental setups. The proposed approach is almost completely automated and therefore a good candidate for being integrated in data analysis flows in labs where the machine learning expertise required to tune traditional classifiers might not be available.

IT is with great pleasure that we introduce this special section on Chips and Architectures for Emerging Technologies and Applications to the audience of the IEEE Transactions on Computers. We are currently witnessing a technology advancement which is making the gap between the present and future much narrower than it has ever been. The purpose of this special section is to showcase highly innovative, creative, and futuristic chip architectures and functionalities that can range from new paradigms in reconfigurable systems architectures, to adaptive, organic, ubiquitous, and biologically inspired computing, to new classes of chip implants, or any other highly innovative human-to-computer interface. This special section includes two papers, which we hope will offer an interesting perspective on the challenges involved in designing integrated circuits and architectures that leverage the capabilities of emerging technologies in novel applications. The first paper, ‘‘Exploring the Potential of Threshold Logic for Cryptography-Related Operations,’’ by Alessandro Cilardo, investigates the application of a non-Boolean computational paradigm to cryptographic applications. More specifically, the author demonstrates the power of linear Threshold Logic functions, which are enabled by new technologies such as Resonant Tunneling Diodes (RTDs), Single-Electron Tunneling (SET), Quantum Cellular Automata (QCA), and Tunneling Phase Logic (TPL), towards performing fundamental cryptographic operations. An architecture for implementing such operations, namely a Montgomery modular reduction and multiplication, is also introduced and its intrinsic superiority to traditional Boolean computational models in demonstrated. The second paper, ‘‘3D Integration of CMOL Structures for FPGA Applications,’’ by Z. Abid, Ming Liu, and Wei Wang, introduces a combination of hybrid CMOS/ nanoelectronic (CMOL) circuits and 3D integration, in order to develop a 3D CMOL technology with particular emphasis on designing Field-Programmable Gate-Array (FPGA) chips. The authors discuss the architecture, 3D integration, defect tolerance and performance aspects of this technology, as well as its breakthrough potential for developing the next generation of FPGAs. We would like to thank the previous editor-in-chief of the IEEE Transactions on Computers, Dr. Fabrizio Lombardi, for suggesting that we organize this special section, the current editor-in-chief Dr. Albert Y. Zomaya, for hosting this section, and all of the editorial staff for the support in the making of the issue. Additionally, we would like to thank the authors of the submitted papers and the numerous reviewers whose contributions made this special section possible.

Despite great advances in discovering cancer molecular profiles, the proper application of microarray technology to routine clinical diagnostics is still a challenge. Current practices in the classification of microarrays' data show two main limitations: the reliability of the training data sets used to build the classifiers, and the classifiers' performances, especially when the sample to be classified does not belong to any of the available classes. In this case, state-of-the-art algorithms usually produce a high rate of false positives that, in real diagnostic applications, are unacceptable. To address this problem, this paper presents a new cDNA microarray data classification algorithm based on graph theory and is able to overcome most of the limitations of known classification methodologies. The classifier works by analyzing gene expression data organized in an innovative data structure based on graphs, where vertices correspond to genes and edges to gene expression relationships. To demonstrate the novelty of the proposed approach, the authors present an experimental performance comparison between the proposed classifier and several state-of-the-art classification algorithms.

This paper proposes an innovative data structure to be used as a backbone in designing microarray phenotype sample classifiers. The data structure is based on graphs and it is built from a differential analysis of the expression levels of healthy and diseased tissue samples in a microarray dataset. The proposed data structure is built in such a way that, by construction, it shows a number of properties that are perfectly suited to address several problems like feature extraction, clustering, and classification.

This paper proposes a new and very flexible data model, called Gene Expression Graph (GEG), for genes expression analysis and classification. Three features differentiate GEGs from other available microarray data representation structures: (i) the memory occupation of a GEG is independent of the number of samples used to built it; (ii) a GEG more clearly expresses relationships among expressed and non expressed genes in both healthy and diseased tissues experiments; (iii) GEGs allow to easily implement very efficient classifiers. The paper also presents a simple classifier for sample-based classification to show the flexibility and user-friendliness of the proposed data structure.

Memory testing commonly faces two issues: the characterization of detailed and realistic fault models, and the definition of time-efficient test algorithms to detect them. March tests have proven to be a fast, simple and regularly structured class of memory test algorithms. This paper proposes a new polynomial algorithm to automatically generate march tests. The formal model adopted to represent memory faults allows the definition of a general methodology to deal with both static, dynamic and linked faults.

Core-based design and reuse are the two key elements for an efficient system-on-chip (SoC) development. Unfortunately, they also introduce new challenges in SoC testing, such as core test reuse and the need of a common test infrastructure working with cores originating from different vendors. The IEEE 1500 Standard for Embedded Core Testing addresses these issues by proposing a flexible hardware test wrapper architecture for embedded cores, together with a core test language (CTL) used to describe the implemented wrapper functionalities. Several intellectual property providers have already announced IEEE Standard 1500 compliance in both existing and future design blocks. In this paper, we address the problem of guaranteeing the compliance of a wrapper architecture and its CTL description to the IEEE Standard 1500. This step is mandatory to fully trust the wrapper functionalities in applying the test sequences to the core. We present a systematic methodology to build a verification framework for IEEE Standard 1500 compliant cores, allowing core providers and/or integrators to verify the compliance of their products (sold or purchased) to the standard.

This paper proposes an analytical method to assess the soft-error rate (SER) in the early stages of a System-on-Chip (SoC) platform-based design methodology. The proposed method gets an executable UML (Unified Modeling Language) model of the SoC and the raw softerror rate of different parts of the platform as its inputs. Soft-errors on the design are modeled by disturbances on the value of attributes in the classes of the UML model and disturbances on opcodes of software cores. The Dynamic behavior of each core is used to determine the propagation probability of each variable disturbance to the core outputs. Furthermore, the SER and the execution time of each core in the SoC and a Failure Modes and Effects Analysis (FMEA) that determines the severity of each failure mode in the SoC are used to compute the System-Failure Rate (SFR) of the SoC.

Static linked faults are considered an interesting class of memory faults. Their capability of influencing the behavior of other faults causes the hiding of the fault effect and makes test algorithm design and validation a very complex task. This paper presents a memory fault simulator architecture targeting the full set of linked faults

Yield and reliability are two key factors affecting costs and profits in the semiconductor industry. Stress testing is a technique based on the application of higher than usual levels of stress to speed up the deterioration of electronic devices and increase yield and reliability. One of the standard industrial approaches for stress testing is high temperature burn-in. This work proposes a full-scan circuit ATPG for dynamic burn-in. The goal of the proposed ATPG approach is to generate test patterns able to force transitions into each node of a full scan circuit to guarantee a uniform distribution of the stress during the dynamic burn-in test

Static linked faults are considered an interesting class of memory faults. Their capability of influencing the behavior of other faults causes the hiding of the fault effect and makes test algorithm design a very complex task. A large number of March tests with different fault coverage have been published and some methodologies have been presented to automatically generate March tests. In this paper we present an approach to automatically generate March tests for static linked faults. The proposed approach generates better test algorithms then previous, by reducing the test length

Linked faults are considered an interesting class of memory faults. Their capability of influencing the behavior of other faults causes the hiding of the fault effect and makes test algorithm design a very complex task. Although several March tests have been developed for the wide memory faults spread, a few of them are able to detect linked faults. In the present paper March AB, a March test targeting the set of realistic memory linked fault is presented. Comparison results show that the proposed March test provides the same fault coverage of already published algorithms but, it reduces the test complexity and therefore the test time. Moreover, a complete taxonomy of linked faults will be presented

The effect of single-event transients (SETs) (at a combinational node of a design) on the system reliability is becoming a big concern for ICs manufactured using advanced technologies. An SET at a node of combinational part may cause a transient pulse at the input of a flip-flop and consequently is latched in the flip-flop and generates a soft-error. When an SET conjoined with a transition at a node along a critical path of the combinational part of a design, a transient delay fault may occur at the input of a flip-flop. On the other hand, increasing pipeline depth and using low power techniques such as multi-level power supply, and multi-threshold transistor convert almost all paths in a circuit to critical ones. Thus, studying the behavior of the SET in these kinds of circuits needs special attention. This paper studies the dynamic behavior of a circuit with massive critical paths in the presence of an SET. We also propose a novel flip-flop architecture to mitigate the effects of such SETs in combinational circuits. Furthermore, the proposed architecture can tolerant a single event upset (SEU) caused by particle strike on the internal nodes of a flip-flop

New memory production modern technologies introduce new classes of faults usually referred to as dynamic memory faults. Although some hand-made March tests to deal with these new faults have been published, the problem of automatically generate March tests for dynamic faults has still to be addressed, in this paper we propose a new approach to automatically generate March tests with minimal length for both static and dynamic faults. The proposed approach resorts to a formal model to represent faulty behaviors in a memory and to simplify the generation of the corresponding tests.

Among the different types of algorithms proposed to test static random access memories (SRAMs), March tests have proven to be faster, simpler and regularly structured. New memory production technologies introduce new classes of faults usually referred to as dynamic memory faults. A few March tests for dynamic fault, with different fault coverage, have been published. In this paper, we propose new March tests targeting unlinked dynamic faults with lower complexity than published ones. Comparison results show that the proposed March tests provide the same fault coverage of the known ones, but they reduce the test complexity, and therefore the test time.

Technology constantly follows the needs of the marketplace. The current trend of producing digitally-aware environments keeps growing, and it is very likely that in the future we will be surrounded by many heterogeneous devices which communicate each other through distributed and wireless interfaces. We will see a new society of digital systems, whose individuals will be ubiquitous and heterogeneous systems interacting together and providing high productivity and great flexibility. Two technologies seem to be emerging to support this new paradigm: mobile data agents to handle the complexity and heterogeneity of networked infrastructures, and real-time reconfigurable systems to implement flexible, adaptable, and high performance individuals. This paper analyzes how the innovative aspects of these new technologies could be exploited to implement innovative and efficient test and repair strategies

We present some ideas and experiments on using microagents for testing and repairing a distributed system, whose elements may or may not have embedded BIST (built in self test) and BISR (built in self repair) facilities. The microagents are software modules that perform monitoring, diagnosis and repair of the faults. They form together a society whose members communicate, set goals and solve tasks. The platforms taken into consideration for mobile tester microagents include Java Micro Edition, BREW, Symbian, PalmOS, as well as more general small scale platforms. Experimental tester agents in Java 2 Micro Edition and PalmOS are also presented, a solution that ensures portability, flexibility, but also a relatively small memory footprint.

A watchdog processor for the MOTOROLA M68040 microprocessor is presented. Its main task is to protect from transient faults caused by SEUs the transmission of data between the processor and the system memory, and to ensure a correct instructions' flow, just monitoring the external bus, without modifying the internal architecture of the M68040. A description of the principal procedures is given, together with the method used for monitoring the instructions' flow.

The tool described in this paper aims at evaluating the effectiveness of software-implemented fault-tolerant techniques used in safety-critical systems. The target application is stressed with the injection of transient or permanent faults. The user can therefore observe the real behaviour of the application in presence of a fault, and, if necessary, take the appropriate countermeasures. The accent is put on the extreme easiness of the use and the portability on all UNIX platforms.

Today, in the world, there are more embedded systems then people. The use of digital systems pervades all areas of our lives, and this trend of producing digitally-aware environments will keep growing. In the future it will be normal to live surrounded by large numbers of heterogeneous devices, from domestic systems to complex applications like automotive, transportations, and medical control systems, which will communicate together through distributed and wireless interfaces. These complex heterogeneous digital systems will provide higher productivity and greater flexibility, but it is also accepted that they will not be fault-free. Moreover, the percentage of faults detected by any Endof-Production test will not be enough to guarantee the level of availability and reliability required by the market. In this context, the ability of a complex digital system to detect and possibly correct a fault (self-healing) plays a critical role. The state-of-the-art of the research in digital systems’ self-healing has only recently started to address this problem from a system-level point of view.

In safety-critical applications it is often possible to exploit software techniques to increase system's fault- tolerance. Common approaches are based on data redundancy to prevent data corruption during the software execution. Duplicating most critical variables only can significantly reduce the memory and performance overheads, while still guaranteeing very good results in terms of fault-tolerance improvement. This paper presents a new methodology to compute the criticality of variables in target software applications. Instead of resorting to time consuming fault injection experiments, the proposed solution is based on the run- time analysis of the variables' behavior logged during the execution of the target application under different workloads.

This paper presents a new fault simulator architecture for RAM memories. The key features of the proposed tool are: (1) user-definable fault models, test algorithm, and memory architecture; (2) very fast simulation algorithm; (3) ability to compute the coverage of any provided test sequence with respect to a user-defined set of fault models, and to eliminate redundant operations; (4) assessment of the power consumption generated by the test application. Moreover, the tool is able to modify the test algorithm in order to guarantee the compliance to user-defined power consumption constraints.

In this paper, we analyze the use of UML as a starting point to go from design issues to end of production testing of complex embedded systems. The first point is the analysis of the big gap between system signals and UML messages; then the paper focuses on the additional information necessary to fill such gap; different test types are considered, focusing on the application software test; finally the actuation and observation are both analyzed inside the test environment, with particular care to the black-box requirement for behavioral testing. The emphasis of the work is on the resulting test engine definition, verified on a complex case study of a top-of-the-line automotive application; this application is a modern car console, grouping many controls of car-related devices, such as phone, navigation, radio, CD. The testing of GSM capabilities of such device is studied in particular.

Among the different types of algorithms proposed to test random access memories (RAM), March tests have proven to be faster, simpler, regularly structured and linear in complexity. A March test consists of a sequence of March elements, each composed of a sequence of basic read/write operations to be performed on each cell of the memory, in either ascending or descending order, before proceeding to the next memory cell. The complexity of a March test is given by the number of memory operations in all March elements performed on each memory cell. This paper presents an innovative algorithm for the automatic generation of March tests. The proposed approach is able to generate an optimal March test for an unconstrained set of memory faults in very low computation time.

Starting from the idea of a general methodology to transform design specifications into system level functional test patterns for complex embedded systems, we propose a layered architecture as basis of such process. The architecture aims at strongly simplifying the test design, allowing the test engineer to concentrate on the high level parts of the system and wrapping all the complexity of the test environment. The results are then verified on a complex case study of automotive applications.

Control flow errors have been widely addressed in literature as a possible threat to the dependability of computer systems, and many clever techniques have been proposed to detect and tolerate them. Nevertheless, it has never been discussed if the overheads introduced by many of these techniques are justified by a reasonable probability of incurring control flow errors. This paper presents a static executable code analysis methodology able to compute, depending on the target microprocessor platform, the upper-bound probability that a given application incurs in a control flow error.

This paper presents an attempt of using intelligent agents for testing and repairing a distributed system, whose elements may or may not have embedded BIST (built-in self-test) and BISR (built-in self-repair) facilities. The agents are software modules that perform monitoring, diagnosis and repair of the faults. Together they form a society whose members communicate, set goals and solve tasks. To demonstrate the idea we used the Zeus agent development environment. Two examples of distributed systems are presented in order to illustrate the cooperative model for fault diagnosis and repair.

The emerging field of self-repair computing is expected to have a major impact on deployable systems for space missions and defense applications, where high reliability, availability, and serviceability are needed. In this context, RAM (random access memories) are among the most critical components. This paper proposes a built-in self-repair (BISR) approach for RAM cores. The proposed design, introducing minimal and technology-dependent overheads, can detect and repair a wide range of memory faults including: stuck-at, coupling, and address faults. The test and repair capabilities are used on-line, and are completely transparent to the external user, who can use the memory without any change in the memory-access protocol. Using a fault-injection environment that can emulate the occurrence of faults inside the module, the effectiveness of the proposed architecture in terms of both fault detection and repairing capability was verified. Memories of various sizes have been considered to evaluate the area-overhead introduced by this proposed architecture.

This paper presents an innovative algorithm for the automatic generation of March tests. The proposed approach is able to generate an optimal March test for an unconstrained set of memory faults in very low computation time. Moreover, we propose a new complete taxonomy for memory read faults, a class of faults never carefully addressed in the past.

The present paper explains a new approach to program control flow checking. The check has been inserted at source-code level using a signature methodology based on regular expressions. The signature checking is performed without a dedicated watchdog processor but resorting to inter-process communication (IPC) facilities offered by most of the modern operating systems. The proposed approach allows very low memory overhead and trade-off between fault latency and program execution time overhead.

The paper presents a detailed error analysis and classification of the behavior of an open-source router when affected by Single Event Upsets (SEUs). The experimental results have been gathered on a real communication network, resorting to an ad-hoc Fault Injection system. The injector has been designed to corrupt the router during its normal service and to analyze the SEU injection effects on the overall distributed system. The performed experiments allowed the authors to identify the most critical memory regions and to cluster the router variables according to their impact on system dependability.

In this paper, we propose the use of a UML methodology to go from user requirements and specifications to end of production testing of complex embedded systems. We consider behavioral, structural and physical levels building a comprehensive and modular model. The process contains the definition of a set of properties being created and then updated in each phase, and heavily relies on message passing and elaborating facilities to increase both abstraction and descriptive power. Result of the process is test pattern generation using custom ATE commands. We also present and discuss an underdevelopment case study of a significantly complex automotive application.

The paper proposes a C/C++ source-to-source compiler able to increase the dependability properties of a given application. The adopted strategies are based on two main techniques, code re-ordering and variables duplication. The proposed approach is portable to any platform, it can be applied to any C/C++ source code, and it introduces code modifications that are transparent to the original program functionality. The RECCO tool, which fully automates the process, allows the user to trade-off between the level of dependability improvement and the performance degradation due to the code modification.

This paper presents the integration of a proprietary hierarchical and distributed test access mechanism called HD/sup 2/BIST and a BIST insertion commercial tool. The paper briefly describes the architecture and the features of both the environments and it presents some experimental results obtained on an industrial SoC.

This paper presents a fault injection tool developed to evaluate different DSP-based architectures for space applications. The evaluation addresses mainly the ability of the different architectures to detect Single-Event-Upset (SEU) faults induced by space radiation.

Proposes HD/sup 2/BIST, a complete hierarchical framework for BIST scheduling, data patterns delivering, and diagnosis of a complex system including embedded cores with different test requirements as full scan cores, partial scan cores, or BIST-ready cores. The main goal of HD/sup 2/BIST is to maximize and simplify the reuse of the built-in test architectures, giving the chip designer the highest flexibility in planning the overall SoC test strategy. HD/sup 2/BIST defines a test access method able to provide a direct "virtual" access to each core of the system, and can be conceptually considered as a powerful complement to the P1500 standard, whose main target is to make the test interface of each core independent from the vendor.

This paper presents a BIST architecture, based on a single microprogrammable BIST processor and a set of memory wrappers, designed to simplify the test of a system containing many distributed multi-port SRAMs of different sizes (number of bits, number of words), access protocol (asynchronous, synchronous), and timing.

In this paper we present DSDK/sup 1/, a Dependable Software Development Kit designed to support the software engineer in releasing dependable applications for embedded systems, starting from either commercial or native software. The proposed kit integrates four different tools: RECCO, a source-to-source compiler able to transform any C/C++ native source code in a more dependable version of the same code, WRAP a tool able to wrap executable software modules and transparently enhance their dependability characteristic, EXEM, an external world and device emulator fool, and BOND, a powerful Fault Injection environment able to emulate the occurrence of different types of faults in the system and to evaluate the dependability properties of the overall system. Experimental results gathered on an embedded system running Embedded NT OS demonstrate the effectiveness and the flexibility of the tool.

This paper proposes HD-BIST, a complete framework to support the definition of the scheduling strategy and mechanism of the BISTed blocks of a complex system. Three different layers are presented, to define the HD-BIST approach in terms of a set of high-level BIST scheduling primitives, a communication protocol, and a possible hardware implementation, respectively.

This paper presents the test strategy adopted at different hierarchical abstraction levels (from board to die level) during the development of a multichannel data acquisition and signal processing MCM, designed for the new generation experiments of high-energy physics on the Large Hadron Collider accelerator at CERN.

In digital systems design, strict reliability constraints usually impose very low fault latency and high degree of fault detection of permanent and transient faults. In particular, memory modules, as either devices or IP cores, appeared as one of the most critical parts. This paper presents an advanced on-line memory BIST architecture implemented as an IP core developed for telecommunication applications. A fault latency reduction architecture, a code-based fault detection scheme, and an architecture-based fault avoidance have been composed to meet the required reliability constraints.

Evaluating the faulty behaviour of low-cost microprocessor-based boards is an increasingly important issue, due to their usage in many safety critical systems. To address this issue, the paper describes a software-implemented fault injection system based on the trace exception mode available in most microprocessors. The architecture of the complete fault injection environment is proposed, integrating modules for generating a fault list, for performing their injection and for gathering the results, respectively. Data gathered from some sample benchmark applications are presented The main advantages of the approach are low cost, good portability, and high efficiency.

Evaluating the faulty behavior of low-cost embedded microprocessor-based boards is an increasingly important issue, due to their adoption in many safety critical systems. The architecture of a complete Fault Injection environment is proposed, integrating a module for generating a collapsed list of faults, and another for performing their injection and gathering the results. To address this issue, the paper describes a software-implemented Fault Injection approach based on the Trace Exception Mode available in most microprocessors. The authors describe EXFI, a prototypical system implementing the approach, and provide data about some sample benchmark applications. The main advantages of EXFI are the low cost, the good portability, and the high efficiency