A new class of fault simulation algorithms, that have recently been developed for gate-level fault simulation and shown to have several advantages over concurrent fault simulation, are adapted for switch-level fault simulation.High speed compiled switch-level simulation is used for circuit evaluation that approaches the speed of gate-level simulation.The fault simulation algorithms are single fault propagation, differential fault simulation, active fault simulation and parallel active fault simulation.Using these algorithms, minimum memory requirements and high simulation efficiency are achieved, both of which are essential to performing practical fault simulation at the switch-level due to the large number of switch-level faults.

A mixed functional/IDDQ testing methodology is presented for detecting transistor faults in CMOS VLSI circuits. A fault preprocessor and a fast switch-level fault simulator have been developed for implementing this testing methodology. The fault preprocessor performs fault generation and collapsing of CMOS transistor faults and identifies those transistor faults that are undetectable by functional testing. Faults that are detectable by functional testing are simulated by the switch-level fault simulator using logic monitoring of the circuit outputs. Faults that are deterministically undetectable by functional testing are considered for detection by monitoring the IDDQ current. These faults are detected if they create conducting transistor paths between VDD and GND, thus elevating IDDQ. By using accurate electrical evaluation techniques of the switch-level circuit state the number of faults that are determined to be detectable by functional testing is increased and the corresponding number of faults requiring IDDQ testing is decreased. This decreases the number of test vectors where IDDQ testing is required and therefore minimizes the total test time.

A novel switch-level fault simulation method is presented for MOS circuits that combines compiled switch-level simulation techniques with functional fault modeling. The simulator models both node stuck-at-zero, stuck-at-one faults and transistor stuck-on, stuck-open faults. During compilation the switch-level circuit components are compiled into functional models. The effect of transistor faults on the function of the circuit components is modeled by functional fault models that execute very fast during simulation. The differential fault simulation algorithm developed for gate-level circuits is adapted for use at the switch-level and is shown to perform well, although it incurs a higher overhead due to the dynamic memory properties of MOS circuits.>