Background: Live coding, or the process of instructors writing code in real time in front of students, is an alternative teaching method to showing students static code examples. Variations of live coding tightly coupled with more active learning approaches are common, which can make it difficult to understand the contribution of live coding alone.

One of the major overheads in reconfigurable computing is the time it takes to reconfigure the devices in the system. This overhead limits the speedups possible in this exciting new paradigm. In this paper me explore one technique for reducing this overhead: the compression of configuration datastreams. We develop an algorithm, targeted to the decompression hardware imbedded in the Xilinx XC6200 series field-programmable gate array architecture, that can radically reduce the amount of data needed to transfer during reconfiguration. This results in an overall reduction of about a factor of four in total bandwidth required for reconfiguration.

One of the major overheads in reconfigurable computing is the time it takes to reconfigure the devices in the system. This overhead limits the speedups possible in this exciting new paradigm. In this paper we explore one technique for reducing this overhead: the compression of configuration datastreams. We develop an algorithm, targeted to the decompression hardware imbedded in the Xilinx XC6200 series FPGA architecture, that can radically reduce the amount of data needed to transfer during reconfiguration. This results in an overall reduction of almost 4 in total bandwidth required for reconfiguration.

In this paper, we study the problem of emulating T G steps of an N G -node guest network, G, on an N H -node host network, H.We call an emulation work-preserving if the time required by the host, T H , is O(T G N G /N H ), because then both the guest and host networks perform the same total work (i.e., processor-time product), ⌰(T G N G ), to within a constant factor.We say that an emulation occurs in real-time if T H ϭ O(T G ), because then the host emulates the guest with constant slowdown.In addition to describing several work-preserving and real-time emulations, we also provide a general model in which lower bounds can be proved.Some of the more interesting and diverse consequences of this work include:(1) a proof that a linear array can emulate a (much larger) butterfly in a work-preserving fashion, but that a butterfly cannot emulate an expander (of any size) in a work-preserving fashion,(2) a proof that a butterfly can emulate a shuffle-exchange network in a real-time work-preserving fashion, and vice versa,(3) a proof that a butterfly can emulate a mesh (or an array of higher, but fixed, dimension) in a real-time work-preserving fashion, even though any O(1)-to-1 embedding of an N-node mesh in an N-node butterfly has dilation ⍀(log N), and (4) simple O(N 2 /log 2 N)-area and O(N 3/ 2 /log 3/2 N)-volume layouts for the N-node shuffle-exchange network.

It is well-known that dedicating one disk's worth of space in a disk array to parity check information can allow the array to tolerate a single failure.More recently, two possible ways of increasing that benefit through the use of additional space for parity check information have been demonstrated: The additional space can be used to allow the array to tolerate more than one disk faihtre without the loss of information (multiple-fault tolerance), or it can be used to speed up the reconstruction of a single failed disk and thus reduce the impact of on-line reconstruction on array performance (using a technique known as par-it~declus tering).However, these two advantages could not be obtained simultaneously.In this paper, we demonstrate for the first time how to divide the benefits of extra space for parity check information arbitrarily between increased fault tolerance and accelerated reconstruction of failed disks.In addition, we give a general lower bound on the space overhead required to protect information in a disk array by storing redundant information that widens the optimality of some known multiple-faulttolerant data layouts.

Have1 and Liebl [1973], and Leighton 119841.' The networks of interest are defined in section 1.3.' For any graph 53, we denote by (%I the number of nodes in %.

We study the most general communication paradigm on a multiprocessor, wherein each processor has a distinct message (of possibly distinct lengths) for each other processor. We study this paradigm, which we call chatting, on multiprocessors that do not allow messages once dispatched ever to be delayed on their routes. By insisting on oblivious routes for messages, we convert the communication problem to a pure scheduling problem. We introduce the notion of a virtual chatting schedule, and we show how efficient chatting schedules can often be produced from efficient virtual chatting schedules. We present a number of strategies for producing efficient virtual chatting schedules on a variety of network topologies.

Recently, parity-declustered layouts have been studied as a tool for reducing the time needed to reconstruct a failed disk in a disk array [6, 11]. Construction of such layouts for large disk arrays generally involves the use of a balanced incomplete block design (BIBD), a type of subset system over the set of disks. This research has been somewhat hampered by the dearth of effective, easily implemented constructions of BIBDs on large sets, and by inefficiencies in some parity-distribution methods that create layouts that are larger than necessary. We make progress on these problems in several ways. In particular, we ffl Demonstrate new BIBD constructions that generalize some previous constructions and yield simpler BIBDs that are optimally small in some cases. ffl Show how relaxing some of the balance constraints on data layouts leads to constructions of approximately-balanced layouts that greatly increase the number of feasible layouts for large arrays. ffl Give a new method for d...

This paper presents simple randomized algorithms for dynamically embedding M-node binary trees in either a butterfly or a hypercube network of N processors. These algorithms are dynamic in the sense that the tree to be embedded may start as one node and grow by dynamically spawning children. The nodes are incrementally embedded as they are spawned. Thus, the algorithm is especially suited for maintaining dynamic tree structures like those in divide-and-conquer and branch-and-bound algorithms. In the embeddings, the paper seeks to optimize the load on the processors of the network, the dilation of the tree edges, and the congestion on the network edges, in order to satisfy the demands of load balancing, process locality, and communication efficiency. The paper begins by presenting a simple level-by-level scheme for dynamically embedding trees in a butterfly network, and by successive modifications. The following results are obtained: 1. An embedding algorithm for the hypercube that achieves dilation 1 and, with high probability, load $O((M /N) + \log N)$. 2. An embedding algorithm for the butterfly that achieves dilation 2 and, with high probability, load $O((M/ N) + \log N)$. 3. An embedding algorithm for the hypercube that achieves dilation $O(1)$ and, with high probability, load $O((M/N) + 1)$ and congestion $O((M/ N) + 1)$. The third embedding simultaneously optimizes load and dilation to within constant factors, optimizing congestion as well when $M = O(N)$. The first two embeddings are also optimal to within constant factors when the tree to be embedded is large (i.e., $M = \Omega (N\log N)$. In addition, this paper proves a lower bound of $\Omega (\sqrt {\log N} )$ dilation for deterministic embedding algorithms that achieve load $O((M/ N) + 1)$, which implies that any embedding algorithm that simultaneously optimizes load and dilation must be randomized.

One of the first theorems on permutation routing, proved by V.E. Benes (1965), shows that give a set of source-destination pairs in an N-node butterfly network with at most a constant number of sources or destinations in each column of the butterfly, there exists a set of paths of lengths O(log N) connecting each pair such that the total congestion is constant. An analogous theorem yielding constant-congestion paths for off-line routing in the shuffle-exchange graph is proved here. The necklaces of the shuffle-exchange graph play the same structural role as the columns of the butterfly in the Benes theorem.>

The problem of dynamically allocating and deallocating local memory resources among multiple users in a parallel or distributed system is considered. The goal is to devise an online allocation algorithm that minimizes both the fraction of unused space due to fragmentation of the memory and the slowdown needed by the system to service user requests. The problem is solved in near-optimal fashion by devising an algorithm that allows the memory to be used to 100% of capacity despite the fragmentation and guarantees that service delays will always be within a constant factor of optimal. The algorithm is completely online (no foreknowledge of user activity is assumed) and can accommodate any sequence of insertions and deletions by the users which does not violate global memory bounds. The results have applications in the domain of parallel disk allocation.>

Article Dynamic tree embeddings in butterflies and hypercubes Share on Authors: T. Leighton M.I.T. Mathematics Department and Laboratory for Computer Science, Cambridge, MA M.I.T. Mathematics Department and Laboratory for Computer Science, Cambridge, MAView Profile , M. Newman M.I.T. Mathematics Department and Laboratory for Computer Science, Cambridge, MA M.I.T. Mathematics Department and Laboratory for Computer Science, Cambridge, MAView Profile , A. G. Ranade Department of EECS, University of California, Berkeley, CA Department of EECS, University of California, Berkeley, CAView Profile , E. Schwabe M.I.T. Mathematics Department and Laboratory for Computer Science, Cambridge, MA M.I.T. Mathematics Department and Laboratory for Computer Science, Cambridge, MAView Profile Authors Info & Claims SPAA '89: Proceedings of the first annual ACM symposium on Parallel algorithms and architecturesMarch 1989 Pages 224–234https://doi.org/10.1145/72935.72959Online:01 March 1989Publication History 23citation365DownloadsMetricsTotal Citations23Total Downloads365Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access