Physically-aware$N$-detect ($PAN$-detect) test improves defect coverage by exploiting defect locality. This paper presents physically-aware test selection (PATS) to efficiently generate$PAN$-detect tests for large industrial designs. Compared to traditional$N$-detect test, the quality resulting from$PAN$-detect is enhanced without any increase in test execution cost. Experiment results from an IBM in-production application-specific integrated circuit demonstrate the effectiveness of PATS in improving defect coverage. Moreover, utilizing novel test-metric evaluation, we compare the effectiveness of traditional$N$-detect and$PAN$-detect, and demonstrate the impact of automatic test pattern generation parameters on the effectiveness of$PAN$-detect.

Physically-aware N-detect attempts to improve the detection characteristics of traditional N-detect by exploiting the localized characteristics of defects. Specifically, in addition to detecting each fault N times, we also require that the physical neighborhood surrounding the target change state as well. In this work, the effectiveness of the physically-aware metric is examined using two approaches. First, tester responses from an in-production IBM chip are analyzed to compare the physically-aware N-detect test with other traditional tests that include stuck-at, IDDQ, logic BIST, and delay tests. Second, diagnostic results from LSI chip failures are utilized to directly compare the traditional and physically-aware N-detect metrics. Results from both experiments demonstrate the effectiveness of physically-aware N-detect test in detecting defects in modern industrial designs.

Recent trends in the integration of process-, device-, and circuit-modeling tools and the current rapid emergence of Unix-based computing environments of networked workstations and computer engines makes possible user-friendly, task-based CAD systems for technology optimization, characterization, and cell design. The authors discuss these trends and identify opportunities to use technology CAD tools in the development of competitive technologies and products. It is shown that the ability to provide design centering and extreme-case analysis related to process variables has been a key to aggressive design of robust IC products. This capability results from efforts in the early to mid-1980's to establish integrated modeling systems such as MECCA, the application of general-purpose optimization capabilities such as WATOPT and CENTER, and recent advances in open and powerful computing environments (principally Unix-based distributed resources).>

This paper describes a distributed architecture for the flexible interconnection of heterogeneous networks with a number of mini- and micro computers, in a research environment. The interconnected networks include the DARPA Internet, which uses the DoD protocols, and the X25-based networks PSS and SERCNET.