Accurate and timely mapping of different crop types holds significant importance for food security and crop management at regional and global levels. This letter proposes a novel 3-D-crop type mapping (CTM) model based on an unsupervised crop-type mapping technique using satellite image time series (SITS) data and a 3-D convolutional autoencoder (CAE). The study uses a combination of five different vegetation indices: Normalized Difference Vegetation Index (NDVI), Red-Edge Chlorophyll Vegetation Index (RECl), Normalized Difference Red Edge Vegetation Index (NDRE), Green Normalized Difference Vegetation Index (GNDVI), and Visible Atmospherically Resistant Index (VARI) of time series data, along with a 3D-CAE for feature extraction. The model underwent evaluation employing one publicly accessible dataset and one in-house dataset sourced from the PlanetScope instruments. In the case of the in-house dataset, the model has achieved an accuracy of 88.75%, 73.88%, and 93.97% for maize, paddy, and sugarcane, respectively. In the case of the publicly available dataset, the model has achieved an accuracy of 83.71%, 72.81%, and 75.37% for paddy, triticale, and barley, respectively. Our 3D-CTM model demonstrates higher accuracy in mapping the crop types, which can be further utilized for effective management of the agricultural sectors.

Battery-less technology evolved to replace battery usage in space, deep mines, and other environments to reduce cost and pollution. Non-volatile memory (NVM) based processors were explored for saving the system state during a power failure. Such devices have a small SRAM and large non-volatile memory. To make the system energy efficient, we need to use SRAM efficiently. So we must select some portions of the application and map them to either SRAM or FRAM. This paper proposes an ILP-based memory mapping technique for intermittently powered IoT devices. Our proposed technique gives an optimal mapping choice that reduces the system’s Energy-Delay Product (EDP). We validated our system using TI-based MSP430FR6989 and MSP430F5529 development boards. Our proposed memory configuration consumes 38.10% less EDP than the baseline configuration and 9.30% less EDP than the existing work under stable power. Our proposed configuration achieves 20.15% less EDP than the baseline configuration and 26.87% less EDP than the existing work under unstable power. This work supports intermittent computing and works efficiently during frequent power failures.

Batteryless technology evolved to replace battery technology. Nonvolatile memory (NVM)-based processors were explored to store the program state during a power failure. The energy stored in a capacitor is used for a backup during a power failure. Since the size of a capacitor is fixed and limited, the available energy in a capacitor is also limited and fixed. Thus, the capacitor energy is insufficient to store the entire program state during frequent power failures. This article proposes an architecture that assures safe backup of volatile contents during a power failure under energy constraints. Using a proposed dirty block table (DBT) and writeback queue (WBQ), this work limits the number of dirty blocks in the L1 cache at any given time. We further conducted a set of experiments by varying the parameter sizes to help the user make appropriate design decisions concerning their energy requirements. The proposed architecture decreases energy consumption by 17.56%, the number of writes to NVM by 18.97% at last level cache (LLC), and 10.66% at a main-memory level compared to baseline architecture.

Activity recognition has gained attention due to the rapid development of microelectromechanical sensors. Numerous human-centric applications in healthcare, security, and smart environments can benefit from an efficient human activity recognition system. In this paper, we demonstrate the use of a seismic sensor for human activity recognition. Traditionally, researchers have relied on handcrafted features to identify the target activity, but these features may be inefficient in complex and noisy environments. The proposed framework employs an autoencoder to map the activity into a compact representative descriptor. Further, an Artificial Neural Network (ANN) classifier is trained on the extracted descriptors. We compare the proposed framework with multiple machine learning classifiers and a state-of-the-art framework on different evaluation metrics. On 5-fold cross-validation, the proposed approach outperforms the state-of-the-art in terms of precision and recall by an average of 10.68 and 23.36%, respectively. We also collected a dataset to assess the efficacy of the proposed seismic sensor-based activity recognition. The dataset is collected in a variety of challenging environments, such as variable grass length, soil moisture content, and the passing of unwanted vehicles nearby.

PTZ cameras can be an effective replacement for multiple camera networks with their pan-tilt-zoom capability. However, the state of the art scheduling method for the PTZ cameras focuses mainly on tracking, not on coverage. In this paper, we aim to maximize coverage as well as information gain, thus, leading to effective surveillance. Towards this goal, we define an information map that represents the sensitivity of a region. We propose a scheduling algorithm in which the camera visits those states more often that are likely to be more important than others, thus, maximizing information gain. A probabilistic framework is used to maximize information gain and coverage simultaneously. Currently, there are no existing datasets and methods to evaluate PTZ camera scheduling methods. We build a real multi-camera dataset and develop a performance measure for this purpose. Experimental results show that the proposed stochastic scheduling algorithm based on adaptive information gain probability is better than traditional as well as other variants proposed in the paper in terms of information gain as well as coverage.

Internet of Things edge intelligence requires convolutional neural network (CNN) inference to take place in the edge devices itself. ARM big.LITTLE architecture is at the heart of prevalent commercial edge devices. It comprises of single-ISA heterogeneous cores grouped into multiple homogeneous clusters that enable power and performance tradeoffs. All cores are expected to be simultaneously employed in inference to attain maximal throughput. However, high communication overhead involved in parallelization of computations from convolution kernels across clusters is detrimental to throughput. We present an alternative framework called Pipe-it that employs pipelined design to split convolutional layers across clusters while limiting parallelization of their respective kernels to the assigned cluster. We develop a performance-prediction model that utilizes only the convolutional layer descriptors to predict the execution time of each layer individually on all permitted core configurations (type and count). Pipe-it then exploits the predictions to create a balanced pipeline using an efficient design space exploration algorithm. Pipe-it on average results in a 39% higher throughput than the highest antecedent throughput.

Parallel Prefix adders are arguably the most commonly used arithmetic units. They have been extensively investigated at architecture level, register transfer level (RTL), gate level, circuit level as well as layout level giving rise to a plethora of mathematical formulations, topologies and implementations. This paper contributes significantly to the understanding of these parallel prefix adders in a couple of ways. Firstly, it attempts to describe various such parallel prefix adders in elegant and consistent formulations. Secondly, a new family of parallel prefix adders is proposed at architecture level. The estimates of the area-throughput characteristics for an instance of this family are also presented. While the speeds achieved by this instance match those achieved by the state of the art adders, their area characteristics exhibit upto 26% improvement.

There has been a lot of work on finding safest path from source to destination. However, all these works mainly rely on the crime data available through government sources. The works are missing many important factor that affect safety of a route. In this work, we first propose safety measurement score and then show how it can be used for safe navigation. We proposed a comprehensive safety measure that adapts with time according to the user feedback and online crowd-sourced information. We have developed a complete end-to-end system to demonstrate efficacy of the proposed framework.

We propose a reduced-port Register File (RF) architecture for reducing RF energy in a VLIW processor. With port reduction, RF ports need to be shared among Function Units (FUs), which may lead to access conflicts, and thus, reduced performance. Our solution includes (i) a carefully designed RF-FU interconnection network that permits port sharing with minimum conflicts and without any delay/energy overheads, and (ii) a novel scheduling and binding algorithm that reduces the performance penalty. With our solution, we observed as much as 83% RF energy savings with no more than a 10% loss in performance for a set of Mediabench and Mibench benchmarks.

Today energy is an important factor in designing a multiprocessor system. The overall goal of this work is to propose a methodology for design space exploration of VLIW multiprocessors. We have developed a framework which enables us to explore energy - performance trade-off for state of the art VLIW processors and multiprocessors. Our methodology is capable of simultaneously exploring process-processor binding while tuning the individual VLIW processors to support specific operation concurrency requirements of processes bound to it. We extend existing uniprocessor instruction level energy estimation techniques to multiprocessors. The implementation is based on popular public domain tools like IMPACT and SystemC. Its completeness, robustness and efficacy is demonstrated through a case study on MPEG-2 decoder.