EDBT 2026 Demo / reviewers in the wild / expert
Marc A. Rich
dblp:10/3989
· DBLP profile ↗
3ranked-venue papers
3as first author
0since 2021 · last 1983
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Computer networks · 2 · 2 first-authorSystems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer networks
2 papers |
Physical-layer communications · 31% Internet architecture and protocols · 31% Network performance modeling · 24% | |
| Computer graphics and multimedia
1 paper |
Image and video coding · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 100% |
Topics — the 8 heaviest of 9, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Internet architecture and protocols › buffer management
buffer sharing |
0.0 | 1 | 1977 | Buffer Sharing in Computer-Communication Network Nodes · IEEE Trans. Commun. 1977 |
Network performance modeling › queueing analysis
queueing models of computer systems |
0.0 | 1 | 1977 | Buffer Sharing in Computer-Communication Network Nodes · IEEE Trans. Commun. 1977 |
Physical-layer communications › synchronization
phase-locked loop |
0.0 | 1 | 1974 | Designing Phase-Locked Oscillators for Synchronization · IEEE Trans. Commun. 1974 |
Physical-layer communications
synchronization |
0.0 | 1 | 1974 | Designing Phase-Locked Oscillators for Synchronization · IEEE Trans. Commun. 1974 |
Internet architecture and protocols › buffer management
buffer allocation |
0.0 | 1 | 1977 | Buffer Sharing in Computer-Communication Network Nodes · IEEE Trans. Commun. 1977 |
Routing and switching › switching
message switching |
0.0 | 1 | 1977 | Buffer Sharing in Computer-Communication Network Nodes · IEEE Trans. Commun. 1977 |
Network optimization and economics
resource allocation |
0.0 | 1 | 1977 | Buffer Sharing in Computer-Communication Network Nodes · IEEE Trans. Commun. 1977 |
Integrated circuit design
analog and mixed-signal circuits |
0.0 | 1 | 1974 | Designing Phase-Locked Oscillators for Synchronization · IEEE Trans. Commun. 1974 |
Methods — techniques the papers use, named apart from their topics
phase comparator design · 0.0jitter analysis · 0.0queueing analysis · 0.0message-storage approximation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1983 | The Economics of Parallel Testing
Marc A. Rich, Daniel E. Gentry |
ITC | 1 |
| 1977 | Buffer Sharing in Computer-Communication Network NodesabstractThis paper discusses a technique of sharing extra storage buffers among a number of nodes (for example concentrators) or among a number of output lines in a single node (for example, in a message switching center). Buffer sharing can be used to reduce the probability that a message is blocked, while at the same time buffer storage cells can be conserved. In addition, buffer sharing reduces sensitivity to variations in traffic. Although the improvement increases as the size and complexity of the buffer sharing system increases, significant improvement is possible even for relatively simple systems. In modeling these systems, a precise model would use data unit storage. However, a simpler model using message storage is easier to analyze. A linear relationship can be used for converting message storage into data unit storage. Marc A. Rich, Mischa Schwartz |
IEEE Trans. Commun. | 1 |
| 1974 | Designing Phase-Locked Oscillators for SynchronizationabstractPhase-locked oscillators (PLO's) have two main areas of application: demodulation and synchronization. In this tutorial paper, a simplified approach to designing PLO's for synchronization is described. In particular, some tradeoffs which can be made between such characteristics as capture range, jitter attenuation, time to lock, and phase offset are presented. As examples of this approach, the method is applied to three circuits in a Picturephone®video coder-decoder (CODEC). The application of an optimum phase comparator is also described. Marc A. Rich |
IEEE Trans. Commun. | 1 |