This paper presents an implementation of irregular low density parity check decoder using both FPGA and ASIC. The considered low density parity check code has code rate 1/2, codeword length of 8088 bits and parallel factor of 24. The partly parallel structure, memory management, message alignment and addressing generation schemes needed to realize the underlying graph connectivity will be discussed. With the target FPGA device Xilinx XC2V8000 and maximum number of 25 iterations, the information decoding throughput could achieve up to 40 Mbps. By using the same configuration and Texas Instruments' GS-40 0.11 /spl mu/m ASIC process technology, decoder data rate of 188 Mbps could be achieved for this decoder.

In general, encoding for LDPC codes can be difficult to realize efficiently. The paper presents techniques and architectures for LDPC encoding that are efficient and practical for a particular class of codes. These codes are the irregular partitioned permutation LDPC codes recently introduced by the author (Hocevar, D.E., Proc. IEEE Int. Conf. on Commun., p.2708-12, 2003). Since these codes are quasi-cyclic, it is known that a simpler encoding process does exist. The paper goes beyond that basic method by exploiting other structural properties to allow for a simpler and faster encoding process, in both software and hardware. Solutions for some rank deficient codes are also given.

This paper presents an LDPC code construction technique for irregular codes of various block sizes and code rates, thus obtaining the performance benefit of irregular distributions. It represents an extension of the methods presented by Sridhara et al. [2001] for regular codes. More importantly, an efficient and practical decoder architecture is also presented that achieves flexibility in block size and code rate for this broad family of codes, a capability not present in other approaches. This decoder can also achieve a high degree of parallelism, thus exploiting one of the benefits of belief propagation.

We develop a new construction criterion for BSPK space-time codes. Based on this criterion, we propose a new method of improving the performance of space-time codes, namely bit interleaving. Then, we provide a computationally effective, iterative way of decoding bit interleaved space-time codes. At the end, we note the 2 dB gain due to the new approach. A proposed 16 state bit interleaved code operates close to 3 dB from the outage probability.

Starting with an ordinary parallel concatenated turbo encoder in a block fading Rayleigh channel, we introduce bit-interleaving of the outputs, not for time diversity, but to increase the coding gain. We develop a guideline metric for designing QPSK space-time codes which reveals both the coding and diversity advantage of the systems as well as showing that it is unnecessary to guarantee full space diversity to achieve good performance in Rayleigh fading. Using channel a priori information in the MAP iterations for decoding, we achieve frame error rates within 1 dB of the outage probability with only modest increases in decoding complexity.

This paper presents a discussion of a top-down VLSI design approach which involves system level performance modeling, block level cycle based simulation, RTL/VHDL simulation and gate level emulation. An MPEG-2 audio/video decoder design example illustrates the use of this top-down approach. Most of the discussion concentrates on the concept of block level cycle based (BLCB) simulation. HW/SW co-design also played an important role in this work and our approach towards such co-design is discussed as well.

The improvement in computational throughput of VLSI circuit simulation is addressed. A high degree of natural parallelism exists in the circuit simulation problem; potentially a large number of processor can be used efficiently. Three distinct approaches for obtaining parallel execution in direct-method circuit simulators are investigated. These approaches differ primarily in the size of the individual tasks used to obtain parallel execution. The relative advantages of each approach are examined, and performance data from simulations on parallel processing systems are presented. For the third approach, very good parallel efficiency was obtained; in some cases, 99% parallelism has been observed.>

OASYS, a flexible and efficient system for circuit optimization and performance characterization, is presented. This system has been successful in being accepted in an industrial design environment. A unique aspect of this system is the use of distributed computing resources to reduce the computation time. A structured problem specification methodology was developed which is novel in that it provides the user with much flexibility yet allows simplification through libraries. A user-interface and management system has been built which allows multiple jobs to be run and dynamically monitored and altered. This system has received considerable usage industrially.>

To exploit time-domain latency in circuit simulation using direct methods, an accurate, computationally efficient model for slowly moving, dormant portions of the circuit is required. A new, implicit integration method, the overdetermined polynomial method (ODPM), has been developed which permits the formulation of an accurate latent model. Using the ODPM integration method, the Jacobian of a dormant subcircuit need not be reevaluated over a large number of time steps of varying size. An accurate Norton equivalent circuit that emulates the impedance and current characteristics of the subcircuit can be obtained without reevaluation of the Jacobian or nonlinear charge computations. This new approach for utilizing latency produces significant improvements in circuit simulation speed with no decrease in accuracy or generality. The authors have demonstrated speed gains of 3 to 20 times over TISPICE for several large circuits.>

Two techniques are presented for optimizing the parametric yield of digital MOS circuit blocks for VLSI designs. The first is based on quasi-Newton methods and utilizes the gradient of the yield. A novel technique for computing this yield gradient is derived and algorithms for its implementation are discussed. Geometrical considerations motivate the second method which formulates the problem in terms of a minimax problem. Both yield optimization techniques utilize transient sensitivity information from circuit simulations. Encouraging results have been obtained thus far; several circuit examples are included to demonstrate these techniques.>

A system of CAD programs, called SPIDER, for ensuring adequate current-carrying capacity in VLSI circuits has been developed. The approach is hierarchical, and it automates and simplifies many of the tasks previously performed by the circuit designer. The system converts transient current waveforms into dc electromigration equivalent values, and includes an algorithm for determining the line width adjustments necessary for meeting specified median-time-to-failure (MTF) requirements. SPIDER also computes voltage drops with respect to a reference node and calls upon an optimization algorithm for correcting violations of a voltage drop specification.

An integrated and efficient approach is developed for automated statistical circuit design. One major problem in statistical circuit design for MOS VLSI is the prohibitively expensive computational requirements. The objective is to find realistic, accurate, and efficient solutions for use in the MOS VLSI design area. An automated statistical characterization system has been developed to characterize a large number of MOS devices to obtain statistical information on device parameters. A statistical model for MOS VLSI circuits has been developed in which only the interdie variations are considered, since they are much larger than the local intradie variations. Therefore, the set of statistical variables are different from the set of design parameters, and this leads to a resolution of the problem of dimensionality associated with statistical design. In this statistical model, variations in device length and width, oxide capacitance, and flat band voltage, have been shown to be the principal process factors responsible for the statistical variation of device characteristics. A scalable MOS model has been developed to represent changes in the device model parameters as functions of these principal factors. This accurate and simple statistical modeling approach uses only four statistical variables, and thus permits computationally efficient statistical parametric yield estimation (SPYE). The direct approach for transient sensitivity computation has been implemented in SPICE to allow very efficient computation of performance function sensitivities. An efficient technique for computing the yield gradient using the SPYE and transient sensitivity results is discussed and an example is presented to demonstrate its use in parametric yield optimization.

This paper discusses the algorithms and implementation necessary for computing time domain sensitivities during circuit simulation. The adjoint approach and the direct approach have been studied, and it was concluded that the direct approach is the best for implementation. The direct approach allows the transient sensitivities to be computed concurrently in time with the normal simulation, and it has been demonstrated that accurate sensitivity computations can be obtained, by simply allowing the sensitivity circuits to use the same time steps as the original circuit. This implementation also incorporates the charge based model for the MOSFET's and those sensitivity derivations are shown. It has been found that the responses of the sensitivity circuits can be discontinuous, and that this is due to discontinuities in the derivatives of the charge with respect to voltage. Derivations for various performance function sensitivities in terms of the response sensitivities are also given.

This paper is concerned with the computational problem of maximizing the yield of circuits. A statistical Monte Carlo based approach is taken in order to compute yield estimates directly and to decrease dimensionality dependence. The main contribution of this paper is a yield extrapolation technique which is very effective in maximizing the yield along a search direction. This technique is based upon a quadratic model of the circuit. Statistical yield estimates are computed from the model and correlated sampling is used to extrapolate along the search direction. Two simple methods for determining search directions are discussed and these are used to demonstrate the overall method through several examples.

The efficiency of several variance reduction techniques (in particular, importance sampling, stratified sampling, and control variates) are studied with respect to their application in estimating circuit yields. This study suggests that one essentially has to have a good approximation of the region of acceptability in order to achieve significant variance reduction. Further, all the methods considered are based, either explicitly or implicity, on the use of a model. The control variate method appears to be more practical for implementation in a general purpose statistical circuit analysis program. Stratified sampling is the most simple to implement, but yields only very modest reductions in the variance of the yield estimator. Lastly, importance sampling is very useful when there are few parameters and the yield is very high or very low; however, a good practical technique for its implementation, in general, has not been found.