This paper analyzes an effect of inter-wire skew on signal integrity in a multi-channel system and proposes circuit techniques to enhance signal integrity by using a spatially correlated coded signaling (SCCS). Through the in-depth analysis, the paper investigates a relation between skew and insertion loss (IL), and highlights an importance of wide-range inter-wire de-skewing (IWD). The proposed phase interpolator (PI)-based IWD technique adjusts the transition edges of receiver inputs to minimize skew caused by mismatch components, which increases timing jitter. The transceiver employs pseudo-differential signaling to verify the effect of the IWD in SCCS. The transmitter integrates a feed-forward equalizer (FFE) with a latch-based re-timer and a PI for each channel. Additionally, a 3-tap FFE at the transmitter and a continuous-time linear equalizer (CTLE) at the receiver are incorporated to compensate for channel ISI. Fabricated in 40-nm CMOS technology, the proposed 8-channel transceiver achieves an aggregate throughput of 112 Gb/s with a bit error rate (BER) below$10^{\mathbf {-12}}$. The transceiver occupies 0.382 mm2while achieving energy efficiencies of 0.77 pJ/bit/ch for the transmitter and 1.45 pJ/bit/ch for the receiver.

With the increasing computational demands of the neural networks, many hardware accelerators for the neural networks have been proposed. Such existing neural network accelerators often focus on popular neural network types such as convolutional neural networks (CNNs) and recurrent neural networks (RNNs); however, not much attention has been paid to attention mechanisms, an emerging neural network primitive that enables neural networks to retrieve most relevant information from a knowledge-base, external memory, or past states. The attention mechanism is widely adopted by many state-of-the-art neural networks for computer vision, natural language processing, and machine translation, and accounts for a large portion of total execution time. We observe today's practice of implementing this mechanism using matrix-vector multiplication is suboptimal as the attention mechanism is semantically a content-based search where a large portion of computations ends up not being used. Based on this observation, we design and architect A3, which accelerates attention mechanisms in neural networks with algorithmic approximation and hardware specialization. Our proposed accelerator achieves multiple orders of magnitude improvement in energy efficiency (performance/watt) as well as substantial speedup over the state-of-the-art conventional hardware.