Memory bandwidth is frequently a limiting factor in the design of high-speed switches and routers. We introduce a buffering scheme called ping-pong buffering, that increases memory bandwidth by a factor of two. Ping-pong buffering halves the number of memory operations per unit time, allowing faster buffers to be built from a given type of memory. Alternatively for a buffer of given bandwidth, ping-pong buffering allows the use of slower, lower-cost memory devices. But ping-pong buffers have an inherent penalty: they waste a fraction of the memory. Unless additional memory is used, the overflow rate is increased; in the worst case half of the memory is wasted. Although this can be compensated by doubling the size of the memory, this is undesirable in practice. Using simulations, we argue that the problem is eliminated by the addition of just 5% more memory. We show that this result holds over a wide range of traffic and switch types, for low or high offered load, and continues to hold when the buffer size is increased.

In this paper, we consider the behaviors and performances of the three-state-based synchronization mechanisms of DSS in the errored environment. We establish a mathematical model to describe the synchronization mechanisms by employing the sequence space theory, and discuss the behaviors of the two different three-state synchronization schemes-the ITU-T recommended thresholded-counting scheme and the newly proposed windowed-observation scheme. We consider the design guidelines for the synchronization schemes, and finally compare their performances in the cell-based ATM.