Reconfigurable Computers are parallel systems that are designed around multiple general-purpose processors and multiple field programmable gate array (FPGA) chips. These systems can leverage the synergism between conventional processors and FPGAs to provide low-level hardware functionality at the same level of programmability as general-purpose computers. In this work we conduct an experimental study using one of the state-of-the-art reconfigurable computers and a representative set of applications to assess the field, uncover the challenges, propose solutions, and conceive a realistic evolution path. We consider issues of concern including performance/cost. We also consider productivity in the sense of development, compiling, running, and system reliability. It will be shown that for some applications, the performance/cost can be orders of magnitude better than conventional computers. It will be also shown that programming such machines may still require some hardware knowledge, similar to hardware knowledge computer programmers must acquire to write scalable programs.

Applications running on a reconfigurable computer can be divided into two major categories: computationally intensive and input/output intensive. In the first case, the input and output are limited, and therefore the performance of the reconfigurable computer depends primarily on the power of the FPGAs, and the capability to exploit parallelism available in a given application. In the second case, the execution time is dominated by input/output, and therefore, an application cannot process data faster than the speed of its slowest input/output channel. The focus of This work is on developing micro-benchmarks to characterize the behavior of various communication channels within reconfigurable computers for the second class of applications. The paper defines a system of 'paper and pencil' micro-benchmarks for the measurement of maximum throughput and minimum latency in the communication between various components of a generic reconfigurable system. The results help to dynamically characterize a reconfigurable machine and the SRC 6E reconfigurable computer is used as a test case to validate the proposed model.

Summary form only given. Reconfigurable computers (RCs) can leverage the synergism between conventional processors and FPGAs to provide low-level hardware functionality at the same level of programmability as general-purpose computers. In a large class of applications, the total I/O time is comparable or even greater than the computations time. As a result, the rate of the DMA transfer between the microprocessor memory and the on-board memory of the FPGA-based processor becomes the performance bottleneck. We perform a theoretical and experimental study of this specific performance limitation. The mathematical formulation of the problem has been experimentally verified on the state-of-the art reconfigurable platform, SRC-6E. We demonstrate and quantify the possible solution to this problem that exploits the system-level parallelism within reconfigurable machines.

Abstract Job Management Systems (JMSs) efficiently schedule and monitor jobs in parallel and distributed computing environments. Therefore, they are critical for improving the utilization of expensive resources in high‐performance computing systems and centers, and an important component of Grid software infrastructure. With many JMSs available commercially and in the public domain, it is difficult to choose an optimum JMS for a given computing environment. In this paper, we present the results of the first empirical study of JMSs reported in the literature. Four commonly used systems, LSF, PBS Pro, Sun Grid Engine/CODINE, and Condor were considered. The study has revealed important strengths and weaknesses of these JMSs under different operational conditions. For example, LSF was shown to exhibit excellent throughput for a wide range of job types and submission rates. Alternatively, CODINE appeared to outperform other systems in terms of the average turn‐around time for small jobs, and PBS appeared to excel in terms of turn‐around time for relatively larger jobs. Copyright © 2004 John Wiley & Sons, Ltd.

Reconfigurable Computers (RCs) can leverage the synergism between conventional processors and FPGAs to provide low-level hardware functionality at the same level of programmability as general-purpose computers. In a large class of applications, the total I/O time is comparable or even greater than the computations time. As a result, the rate of the DMA transfer between the microprocessor memory and the on-board memory becomes the performance bottleneck even on RCs. In this paper, we perform a theoretical and experimental study of this specific performance limitation for the state-of-the art reconfigurable platform, SRC-6E. We demonstrate and quantify the possible solution to this problem that exploits the system-level parallelism within the reconfigurable machine.

Researchers are currently more interested in searching for fragments that are similar to a query, than a total data item that is similar to a query; the search interest is for "contains", not "is". This paper presents an O(logn) algorithm, called the "generalized virtual node (GVN)" algorithm; the GVN algorithm is a search algorithm for data fragments that have similar contents to that of a query. An example of the use of the GVN algorithm is in the search of an image database for a certain picture object regardless to what their picture backgrounds are. Each image is transformed into characteristic features and these features are stored in a hierarchical multidimensional structure, called a "k-tree." The k-tree is exploited to build a unified retrieval model for any type of multimedia data. The experimental results of this "in-picture" search algorithm on an image database demonstrate a search quality that is qualitatively and quantitatively acceptable, with a retrieval time that is faster than other algorithms, such as brute-force and partial matching.

Article Free Access Share on A new "quad-tree-based" sub-system allocation technique for mesh-connected parallel machines Authors: Jeeraporn Srisawat Department of Electrical Engineering and Computer Science, The George Washington University, Washington, DC Department of Electrical Engineering and Computer Science, The George Washington University, Washington, DCView Profile , Nikitas A. Alexandridis Department of Electrical Engineering and Computer Science, The George Washington University, Washington, DC Department of Electrical Engineering and Computer Science, The George Washington University, Washington, DCView Profile Authors Info & Claims ICS '99: Proceedings of the 13th international conference on SupercomputingJune 1999 Pages 60–67https://doi.org/10.1145/305138.305160Published:01 May 1999Publication History 2citation315DownloadsMetricsTotal Citations2Total Downloads315Last 12 Months12Last 6 weeks4 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

We present a uniform construct of parallel programming for a set of image processing tasks based on our distributed computing primitive (DCP) concept. Our target architecture is a heterogeneous computing network system consisting of various high performance workstations connected through a local area network. We show that DCP has advantages over non-primitive PVM-based parallel approaches in three aspects: ease-of-use, automation, and optimization.

A methodology based on functional programming for the systematic synthesis of problem-oriented architectures is presented. The different ways of sequencing the input data are shown to lead to a variety of alternative architectures for the same computational problem (with the same behavioural description). The finally selected architecture satisfies certain user-defined restrictions and maximises given performance criteria. The presented methodology is applicable to a wide range of computing problems and can be used in the process of designing specialised VLSI systems.

This paper presents an efficient method for transmitting regularly-decomposed pictures which have been coded through an orthogonal Walsh-Hadamard transformation. The regular-decomposition procedure converts the picture into a tree representation and compresses the original amount of data by not retaining non-informative areas of the picture. The Walsh-Hadamard transformation is performed on the regularly-decomposed picture as an averaging or smearing process to allow transmission which is more immune to channel errors. It also makes bandwidth reduction possible because, since the image energy which is usually uniformly distributed in the spacial domain now tends to be concentrated near the origin of the transform domain, some of the low-magnitude samples may be discarded. A conceptual design is given where the three steps of regular-decomposition, Walsh-Hadamard transformation, and transmission, instead of being performed sequentially one after the other, are now carried out simultaneously.

A technique for obtaining the digital Walsh-Hadamard transform of two-dimensional discrete pictures in real time is presented. A considerable reduction in total time for the transformation of a picture results since the process of scanning and digitizing one picture line overlaps with computations on the previous line. This is accomplished by operating on each picture line as it is generated from the scanner, instead of starting the transformation operation after the entire picture has been scanned. Two theorems are presented which decompose a picture by row or by column to facilitate real-time transformation. Based on these theorems, a hardware machine for real-time parallel Walsh-Hadamard transformation is introduced.

Experimental pattern recognition techniques for processing chromosome slides with a computer are described. The purpose of the computer program is twofold: to illuminate the basic mechanisms by which a human recognizes an object, such as a chromosome, and distinguishes it from other entities; and the employment of these mechanisms is an automatic and precise extraction of chromosome features.

A parameter is defined that distinguishes the members of the set\{WAL(s,m)\}of Walsh functions. There is a one-to-one correspondence between sequency and axis symmetry of each Walsh function. Axis symmetry is derived from the sequency number. A procedure is introduced for obtaining the period of a Walsh function from its sequency number.