In this paper, we investigate the opportunities offered by floating-point arithmetics in enabling an assembly and intrinsics free high-level language based development. We compare the characteristics of floating- and fixed-point arithmetics by simulating a MIMO-OFDM soft output detector in a 3G LTE link level simulator. The hardware complexity and energy dissipation are analyzed by implementing three programmable processors supporting 32- and 12-bit floating-point and 16-bit fixed-point arithmetics. The processors are based on the transport triggered architecture (TTA) that has a very low programmability overhead. The analysis shows that at the same goodput rate a floating-point implementation can achieve a lower gate count and better power efficiency than a fixed-point design.

Multiple input multiple output (MIMO) transmission is an emerging technique targeted at 3G long term evolution (LTE) systems. One vital baseband function in MIMO receivers is QR decomposition of the channel matrix. In this paper, a processor based complex-valued QR decomposition is presented. The processor is enhanced with complex arithmetic and inverse square root function units. The proposed processor fits well with the real-time requirements of the MIMO receiver. The computing power is tailored for typical MIMO systems. Due to the generality of the applied computing resources it can also be used for other tasks. Also, the presented principles can be applied on any customizable processor architectures to accelerate QR decomposition.

By exploiting the inherent parallelism in digital signal processing algorithms, significant savings in area and power consumption may be achieved. Completely parallel computation can lead to excessive area, thus mapping the algorithm onto reduced computational resources becomes beneficial. As a drawback, data interconnections become more complex and require storage in order to maintain computationally correct processing. We have proposed a systematic design methodology for managing data interconnections called stride permutations. These stride permutations are found in several algorithms, including fast Fourier transforms and Viterbi decoding. The proposed methodology leads to regular and scalable permutation networks which support power-of-two strides. In addition, the networks reach the lower bound in the number of registers indicating area-efficiency. In this paper, the proposed networks are evaluated in terms of control, area, power consumption, and timing

Fixed-point simulations for inverting matrices using transport triggered architectures are performed. Several methods are implemented in fixed-point: the Cholesky decomposition as a direct method, Newton iterations as an iterative method, and Strassen Newton algorithm as a combined recursive method. Fixed-point implementations of these matrix inversion algorithms are tested and analyzed. A division-free implementation is targeted.

Efficient and flexible Viterbi decoding is an important problem in implementation of modern telecommunications systems. In this paper, a 256-state, rate 1/2 Viterbi decoder is implemented on a transport triggered architecture processor. Due to the processor-based platform, the implementation is flexible and it can achieve relatively high decoding speed. The decoder is implemented by tailoring the processor to meet the requirements of Viterbi decoding. The processor is enhanced with a number of special function units, which accelerate the decoding. As a result, the decoding can be carried out efficiently on a processor-based platform.

A systematic approach for the path metric memory management in Viterbi decoders is presented. Between the parallel computation units and memory modules, a permutation of path metrics is required in order to access the path metrics in correct order. We propose a parallel memory access scheme, which reduces the interconnection complexity between parallel computation units and memory modules by rescheduling the path metric computations.

The computational requirements of turbo decoders are heavy and depend on the number of decoding iterations. However, only a few iterations are often enough for obtaining an error free outcome. Instead of idling during the unused iterations, the released time slots can be used for enabling extra iterations required by the decoding, when the errors are more severe. Since the number of required iterations for each code block is not known beforehand, the allocation of iterations must adapt according to the current demand and the past iterations. In this paper, the dynamic adaptation is achieved by an additional buffering of incoming code blocks and the effect of utilizing unused iterations are studied.

The memory requirements of turbo decoders are high since long code block lengths are preferred. Especially, the extrinsic information memory is accessed frequently with both linear and interleaved access patterns. In this paper, a parallel access scheme into extrinsic information memory is developed for a 3GPP turbo decoder. A single port memory is divided into parallel accessible modules and the memory throughput requirements and both the linear and interleaved access patterns are considered as module and word address generating functions are developed. As a result, the throughput of the parallel access scheme allows high-speed decoding and the usage of the dual port memory can be avoided and savings in chip area are achieved.

In array processors, complex data reordering is often needed to realize the interconnection topologies between the computational nodes in algorithms. Several important algorithms, e.g., discrete trigonometric transforms and Viterbi decoding, can be represented in a radix-R form where the principal topology is stride by R permutation. A general factorialization of stride permutations is derived, which can be mapped onto register-based structures for constructing area-efficient multi-port interconnection networks. The networks can be modified to support several stride permutations and sequence sizes.