This paper reports a new scalable behavioral modeling technique for silicon controlled rectifier (SCR) based electrostatic discharge (ESD) protection structures using Verilog-A language. Accurate models were developed for various low-triggering voltage SCR ESD (LVSCR) protection structures implemented in a foundry 180nm RF process, which were validated by circuit simulation and ESD measurement.

For decades, advances in integrated circuits (IC) have been driven by continuous scaling down of planar IC technologies. As IC scaling rapidly approaches to technical brick wall, 3D IC heterogeneous integration emerges as a viable solution for future integrated electronics. Future complex system-on-a-chip (SoC) requires high-performance active devices, and novel passive and supporting devices. This paper reviews recent advances in develop 3D magnetic-enhanced inductors and 3D on-chip electrostatic discharging (ESD) structures to achieve heterogeneous 3D ICs with high performance and reliability simultaneously.

A nanopower subthreshold bandgap reference with 30ppm/°C from -30°C to 150°C has been implemented in 0.18μm CMOS. This design is based on weighted ΔVGSand is free of resistors. The major advantage of this design is that with nanopower consumption, the temperature range is extremely wide. To achieve high performance of subthreshold bandgap operating in high temperature (above 80°C), a leakage current elimination technique which enables subthreshold bandgap operate properly until 150°C was proposed. Such modification does not require additional die area and power consumption. This topology can also generate multiple reference voltages whose values are integer times of the minimum reference voltage. The line regulation of the reference voltage is 0.677mV/V when the supply voltage is increased from 1 V to 2.5 V. The core circuit consumes 46nW at IV at room temperature. The active area occupies 0.0036mm2.

A low-power full 3.1-10.6 GHz UWB transmitter using very simple 4-delay-cell 5th-derivative Gaussian pulse generation for carrier-free IR-UWB system is designed and fabricated in 0.13 mum CMOS. The fully integrated IR-UWB transmitter features on-chip compensated active balun and simple BPSK modulation. Measurement shows the lowest reported power of 33 pJ/pulse at 100 MHz PRF, short 5th-derivative Gaussian pulse width of 750 ps and Vppof 84 mV. This FCC-compliant IR-UWB transmitter allows up to 1.3 Gbps throughput for low-cost low-power hi-QoS wireless multimedia and video streaming.

A fully integrated, ultra low-power, varying pulse width second-order derivative Gaussian pulse generator designed and fabricated in a commercial 0.18μm CMOS technology is reported for 3-10GHz ultra wideband (UWB) transceivers. The second-order derivative Gaussian pulse generator circuit consists of three cascaded stages for generating square wave, Gaussian impulse, and second-order derivation sequentially. This CMOS second-order derivative Gaussian pulse generator can generate UWB pulses with adjustable pulse width ranging from 220 picoseconds to a few nanoseconds. Measured circuit performance achieves a very short pulse width of <1ns, an amplitude of 70mV and an ultra low power consumption of 2mW at 100MHz pulse repeating frequency. The pulse generator fully complies with FCC power mask.