The lithography process inherently introduces device-to-device variation in the fabrication of resistive random-access memory (RRAM) array, introducing electrical mismatch and limiting the practical applications of RRAM-based analog computing circuits. In this work, we propose a lithography model-aware layout synthesis framework to minimize the proximity effect in the lithography process, thus reducing the electrical mismatch amongst these devices for analog computing applications. A dummy RRAM cell insertion technique is proposed to reduce the geometrical mismatch among RRAM cells, and a bi-objective alternate optimization method is proposed to efficiently optimize the geometric parameters and the structure of RRAM layouts. In addition, an approximation method for evaluating the quality of the RRAM array layout is proposed to reduce the runtime of synthesis. The experimental results show that our proposed framework significantly reduces the deviation between printed and expected patterns.

This paper presents the design of a wideband pipelined multi-stage noise shaping (MASH) continuous time (CT) delta-sigma modulator (DSM). The quantization error of the overall$1^{\mathrm {st}}$-stage DSM is extracted as the input of the$2^{\mathrm {nd}}$stage, while the outputs of both stages are simply combined without using any digital filters. Overall, different shaping functions are generated for both QN without requiring any digital QN cancellation. Therefore, the pipelined MASH (PMASH) significantly mitigates QN leakage while retaining the decent loop stability of a traditional MASH. Additionally, several analyses have been made for the PMASH topology, e.g. the design guideline, the signal transfer function (STF), the robustness, etc. Clocked at 800MHz and enabling on-chip DAC calibration, the 65nm CMOS prototype with an exemplary 2-2 topology using multi-bit quantizers achieves 82.6 dB SNDR, 98.8 dB SFDR over 15.4 MHz BW at −0.5 dBFS 1.8 MHz input. The power consumption is 16.9 mW with 1.2V/1.5V supplies. It results in a competitive FoM${}_{\mathrm {S\vert SNDR}}$of 172.2 dB, while it avoids any off-chip calibrations.

Network-on-Chip (NoC) accelerators with heterogeneous Processing-in-Memory (PIM) cores achieve superior performance than homogeneous ones for neural networks. Dedicated simulators and architecture search frameworks are pivotal for obtaining performance, power, and area (PPA) metrics, as well as guiding the design process. However, existing simulators are primarily designed for homogeneous NoC and lack support for simulating heterogeneous PIM-based NoC architectures. Besides, current search frameworks for heterogeneous NoC architectures only focus on workload allocation and mapping strategies, failing to explore heterogeneous PIM configurations in a larger design space. In this work, we propose HPIM-NoC, a joint simulation and search framework for heterogeneous PIM-based NoC architectures. HPIM-NoC not only supports the simulation of heterogeneous PIM cores, but also provides more accurate latency results by introducing NoC transmission delays and pipelines in co-simulation. HPIM-NoC implements a three-stage heterogeneous search process based on priori knowledge and employs a specific simulated annealing algorithm tailored for heterogeneous architecture search. The search process is accelerated by precomputing core PPA metrics and reducing NoC simulation frequency. In addition, the framework integrates a customized layout algorithm to optimize the placement of heterogeneous NoC, minimizing communication latency and overall area. Experimental results on various neural networks demonstrate that HPIM-NoC can quickly find near-optimal configurations within a limited time. The proposed acceleration method reduces the search time of HPIM-NoC by $2.12 \times$, $2.17 \times$, and $2.96 \times$, respectively. Compared to homogeneous architectures, the Fusions of Metrics (FoMs) of heterogeneous PIM-based NoC architectures found by HPIM-NoC are reduced by $\mathbf{1. 1 8 \%, ~} \mathbf{1 6. 9 4 \%}$, and $\mathbf{3 7. 4 1 \%}$ for ResNet-18 under three settings, respectively.

In this paper, we demonstrate a bi-directional biomedical process-invariant pixel interface based on the LTPS-TFT that integrates a front-end amplifier, an analog-to-digital converter and a stimulator. The pixel interface can convert biopotential into digital signals. This near-sensor signal processing can avoid the interference of motion artifacts, and the all-digital transfer has a high noise tolerance. Under the process variation of 1×-1.4× threshold voltage and ±10% mobility fluctuations, the DC gain of the operational amplifier changes from 58.83 dB to 57.21 dB, and 39.09 dB to 37.88 dB for the front-end amplifier. Compared with the single-stage amplifier, the stability has been improved by 13.2×. The proposed pseudo differential VCO-based ADC can effectively eliminate second-order non-linearity which achieves the best performance in state-of-the-art TFT-ADCs. When the threshold voltage and mobility fluctuate, ENOB changes from 7.36 bit to 7.30 bit (OSR=64) and 11.52 bit to 11.14 bit (OSR=256). The change rate does not exceed 4%.

Unsupervised domain adaption (UDA), which aims to enhance the segmentation performance of deep models on unlabeled data, has recently drawn much attention. In this paper, we propose a novel UDA method (namely DLaST) for medical image segmentation via disentanglement learning and self-training. Disentanglement learning factorizes an image into domain-invariant anatomy and domain-specific modality components. To make the best of disentanglement learning, we propose a novel shape constraint to boost the adaptation performance. The self-training strategy further adaptively improves the segmentation performance of the model for the target domain through adversarial learning and pseudo label, which implicitly facilitates feature alignment in the anatomy space. Experimental results demonstrate that the proposed method outperforms the state-of-the-art UDA methods for medical image segmentation on three public datasets, i.e., a cardiac dataset, an abdominal dataset and a brain dataset. The code will be released soon.

Conventional physics-based memristor device modeling methods highly rely on human expertise, which results in a long development period. To address the aforementioned challenges, we propose a new generalized memristor (GEM) device modeling framework based on the artificial neural network (ANN) technique, which has a minimum dependency on the underlying physics, resulting in a fast turn-around development time for customized memristor devices. GEM framework models the switching and conducting behaviors of the memristor devices separately, avoiding the signal-dependence issue in the prior time-series data modeling method. The result of the GEM framework is a compact model that supports general-purpose circuit simulators. Experimental results show that our compact model achieves a ratio of root-mean-square error to peak-to-peak (RMSE/PP) of 3.6% compared to the physics-based device model. Performance analysis of memristor-based logic and memristor crossbar circuits are conducted to demonstrate the effectiveness of our proposed GEM framework for the design and analysis of memristor-based circuits.

This work introduces a two-channel time-interleaved (TI) continuous-time (CT) 3rd-order delta-sigma modulator (DSM). It uses the information from one complete channel to predict the other channel based on the extrapolation principle. Note that, Cascaded Integrator of Distributed Feedforward (CIFF) topology is selected for the loop filter for the following reasons: 1) it could reduce the number of required feedback DACs as much as possible; 2) it allows to implement the zero optimization for the TI DSM such that the performance could be further improved. Furthermore, we employ the technique of error correction to address the issue regarding the delay-free feedback path, which originates from the extrapolating TI DSM. We present the derivations of the target TI CT DSM starting from a single-channel discrete-time (DT) DSM, while the compensation for excess loop delay (ELD) is considered. Fabricated in 65nm CMOS process, this modulator achieves an equivalent output sampling rate of 800MS/s, while the analog channel operates at 400MHz. It exhibits a signal-to-noise and distortion ratio (SNDR) /spurious-free dynamic range (SFDR)/dynamic range (DR) of 75.5dB/89.7dB/79dB over a 10MHz bandwidth. The total power consumption is 33.73mW from 1.2v/1.8v power supplies. It results in a Schreier Figure of Merit (FoM) of 163.7dB based on DR.

The level shifter (LS) circuit has become an indispensable circuit component in both analog and digital systems. In the past decades, there has been an exponential increase in the academic publications for the LS circuits to improve their performances and their applications. Therefore, this review paper provides a comprehensive study of the LS circuit, ranging from circuit topologies and various design methodologies such as sizing methodology, layout design methodology, circuit evaluation methodology, and testing methodology. Finally, we evaluate the state-of-the-art LS circuits and present their performance metrics.

Concurrent neural signal instrumentation withstanding neural stimulation artifacts is essential for bi-directional neural interfaces to guarantee signal integrity. In this work, different front-end structures and stimulation artifact mitigation techniques are firstly reviewed to benchmark their step response speed. Then, a mixed domain level-crossing scheme is proposed to achieve fast dynamic response with minimized hardware overhead. The benefit of extending the phase detection range of the phase detectors in VCO-based continuous time$\rm \Delta \Sigma $modulators is investigated with stability and noise consideration. Then a shift-register-based phase counter is proposed to extend the phase detectors’s detection range, thereby increase quantization resolution and stability margin for in-band noise optimization. The proposed VCO-based neural front-end was fabricated in a 180 nm CMOS process. The prototype achieves$6.38~\mu $Vrms input-referred noise over 0.5 Hz-10 kHz bandwidth. With a linear input range of 120 mVpp, it exhibits a SNDR of 71.6 dB and a DR of 77.0 dB, which could be further extended up to 100 dB in the artifact adaption mode. Measurements verify that the proposed neural front-end can recover from rail-to-rail differential mode or common mode artifacts within 10$\mu \text{s}$(minimum$6.25~\mu \text{s}$) while the superposed small signal can be recorded uninterruptedly.

This paper presents a continuous-time (CT) 0–4 dual-stage Multi-stAge Noise-sHaping (MASH) Delta-Sigma Modulator (DSM), exhibiting +5dBFS maximum stable amplitude (MSA). In the context of 0–4 MASH topology, the 4-bit CT DSM employed as the second stage only processes 4-bit quantization noise (QN) of the front-end. Though the input signal exceeds the full scale (FS), the second stage still stays stable as long as the signal leakage does not overload it. Such feature guarantees the improved stability over a wider signal input range. In addition, to address the well-known QN leakage issue of MASH topology, we propose to combine the feedforward topology with proportional-integral-based excess loop delay compensation. It ensures high robustness of the proposed 0–4 MASH DSM without requiring any calibration. Additionally, we present an analysis of the anti-aliasing filtering (AAF) for the 0-X MASH DSM. It is found that the overall AAF of the 0-X MASH DSM is contributed from the second stage. Sampled at 400MHz, the 65nm CMOS experimental prototype measures signal-to-noise and distortion ratio (SNDR)/spurious-free dynamic range (SFDR) of 76.7dB/87.3dB over a 10MHz bandwidth with 15.1mW power consumption. Moreover, with achieving +5dBFS MSA, the dynamic range (DR) is extended to be as high as 85dB, resulting in a state-of-the-art Scherier Figure of Merit (FoM) of 173.2dB based on DR.

This paper presents a hybrid CT/DT0-2 multi-stage noise-shaping (MASH) delta-sigma modulator (DSM) with a passive noise-shaping successive approximation register (NSSAR) ADC as the $2^{\mathrm{n}\mathrm{d}}$ stage. The overall architecture is simple and robust. The front-end stage employs the continuous-time (CT) operation to perform coarse quantization and provide inherent anti-aliasing and easy driving. The back-end stage uses a second-order NS-SAR architecture, which excels at PVT robustness, power efficiency, and scaling friendliness. It also results in large relaxation of matching issues between the analog and the digital domains compared with conventional CT-MASH. Behavioral simulation results demonstrate the effectiveness and robustness of the proposed hybrid MASH architecture.

Pulse Arrival Time (PAT) is a significant pulse-transition based feature used for non-invasive Blood Pressure (BP) monitoring. Electrocardiography (ECG) and Photoplethys-mography (PPG) are usually used to measure PAT. These signals have multiple characteristic points that can be used as references for measurement. However, based on maximizing feature-BP correlation, most research attempts are focused on the R-peak of ECG and the characteristic points of the rising curve of the PPG. In this paper, to properly characterize the pulse transition, we study the T-wave of the ECG and the falling curve of the PPG to extract different reference points for PAT measurement. Such features hold significant information about the heart and the aorta, which are directly involved in blood flow and pressure. Consequently, these features can improve BP estimation significantly despite having a lower correlation with BP. The study is assessed based on 2152 subjects from VTLdatabase, an open-source surgical database of vital signals. Previous work based on this dataset yielded a root mean squared error (RMSE) of 11/6.25 mmHg for Systolic/Diastolic BP (SBP/DBP); based on traditional PAT features. By incorporating the newly proposed features, the estimation RMSE was lowered to 6.47/3.55 mmHg for SBP/DBP.

The implementation of a power-efficient neuron array system with high throughput and controllable mismatch plays an important role in power-sensitive applications and brain simulations. This paper presents an array of 48 Integrate-and-Fire neurons with axon-sharing architecture implemented in 55-nm CMOS technology. The combination of log-domain circuits and comparator-sharing in neuron design achieves the integration of 3125 neurons/mm2and power consumption of 5.3 pJ/spike. The proposed time modulated axon-sharing synapse architecture realizes 5500 events/s/neuron unit throughput. A novel background calibration module is integrated to reduce the mismatch between neurons. Simulations presents a 45% improvement in SD of inter-spike interval variation. Finally, we validate the architecture by implementing a spiking neural network for solving a 3-stage Sudoku Puzzle. 100% success rate is obtained after calibration.

The design and verification of memristor crossbar circuits and systems demand computationally efficient models. The conventional device-level memristor model with a circuit simulator such as simulation program with integrated circuit emphasis (SPICE) to solve a memristor crossbar is time exhaustive. Hence, we propose a neural network-based memristor crossbar modeling method, XBarNet. By transforming memristor crossbar modeling to pixel-to-pixel regression, XBarNet avoids the iterative procedure in the conventional SPICE method, accelerating the runtime significantly. Meanwhile, XBarNet models the interconnect resistance and nonlinear$I-V$effect of memristor crossbars, which minimizes the simulation errors. We first propose a feature extraction method to bridge a memristor crossbar circuit and a neural network. Then, the network based on the convolutional autoencoder architecture is developed and the filter pruning technique is applied onto XBarNet to reduce the runtime computational cost. The experimental result shows our proposed XBarNet achieves over$78\times $runtime speed up and$1.7\times $memory reduction with only 0.28% relative error comparing to the SPICE simulator.

Embedded arrhythmia classification is the first step towards heart diseases prevention in wearable applications. In this paper, a robust arrhythmia classification algorithm, NEO-CCNN, for wearables that can be implemented on a simple microcontroller is proposed. The NEO-CCNN algorithm not only detects QRS complex but also accurately locates R-peak with the help of the proposed adaptive time-dependent thresholding technique, improving the accuracy and sensitivity in arrhythmia classification. An optimized compact 1D-CNN network (CCNN) with 9,701 parameters is used for classification. A QRS complex augmentation method is introduced in the training process to cater for R-peak location error (RLE). A nested k1k2-fold cross-validation method is utilized to evaluate the robustness of the proposed algorithm. Simulation results show that the proposed algorithm has the ability to detect more than 99.79% of R peaks with an RLE of 7.94 ms for the MIT-BIH database. Implemented on the STM32F407 microcontroller, NEO-CNN attains a classification accuracy of 97.83% and sensitivity of 96.46% using only 8s window size.

Photoplethysmography (PPG) is one of the widely used noninvasive heart rate (HR) monitoring techniques in wearable devices. Lighting of the LED dominates the power consumption of a PPG sensor. Lowering the LED lighting duration is an effectively approach to save power. This paper proposes an adaptive heartbeat locked loop (AHBLL) technique, which can dynamically adjust the dividing ratio N according to the heart rate derivative (HRD). In this way, the LED pulse duty cycle can be significantly reduced to save power. To improve the robustness of the AHBLL system, the relationship between HRD and the dividing ratio N is theoretically analyzed, which provides an optimal design guideline. To verify the proposed technique, an HR sensing circuit including an HRD detector is designed and simulated. The results show that the LED power consumption is reduced by 2.2~3.3× compared with the state-of-the-art heartbeat locked loop (HBLL) technique.

This paper presents a discrete-time multi-stage noise shaping (MASH) delta-sigma modulator (DSM) with second-order digital noise coupling for wideband highresolution applications. By directly injecting the output of the second loop into the quantizer input of the first loop while choosing an appropriate signal transfer function of the second loop, a second-order digital noise coupling can be easily constructed without almost imposing any hardware complexity. With the help of the second-order digital noise coupling, the inherent quantization noise leakage in the MASH topology is significantly mitigated, thus resulting in less DC gain requirement for the integrators. Mathematical analysis and further simulation results are presented to demonstrate the effectiveness of the proposed MASH structure.

The conventional mapping method between RRAM array and convolutional weights faces two key challenges: 1) nonoptimal energy efficiency and 2) RRAM's temporal variation. To address these challenges, we propose shift and duplicate kernel (SDK) convolutional weight mapping architecture. Each kernel is duplicated multiple times and rearranged on different bitlines in a shifted manner, enabling higher intralayer computational parallelism, and reducing the number of input data loading. Hence, this architecture reduces the computational latency and energy consumption in both forward and backward propagation phases. Furthermore, we have introduced a parallel-window size allocation algorithm and a kernel synchronization method. Our proposed parallel-window size allocation algorithm aims to balance the interlayer pipeline architecture, thus improving the overall energy efficiency and area efficiency. Our proposed kernel synchronization method uses an averaging method to suppress the effect of temporal variation during weight update, enhancing the system's robustness for training. From our experiment results, our proposed architecture achieves ~6.8× area efficiency and ~2.1× energy efficiency over the conventional interlayer pipeline architecture. Significant improvement in classification accuracy by 21.7% under a temporal variation of 1%-5% is achieved during on-chip training task on the Cifar-10 dataset.

For the problem of early detection of atrial fibrillation (AF) from electrocardiogram (ECG), it is difficult to capture subject-invariant discriminative features from ECG signals, due to the high variation in ECG morphology across subjects and the noise in ECG. In this paper, we propose an Discrete Biorthogonal Wavelet Transform (DBWT) Based Convolutional Neural Network (CNN) for AF detection, shortly called DBWT-AFNet. In DBWT-AFNet, rather than directly feeding ECG into CNN, DBWT is used to separate sub-signals in frequency band of heart beat from ECG, whose output is fed to CNN for AF diagnosis. Such sub-signals are better than the raw ECG for subject-invariant CNN representation learning because noisy information irrelevant to human beat has been largely filtered out. To strengthen the generalization ability of CNN to discover subject-invariant pattern in ECG, skip connection is exploited to propagate information well in neural network and channel attention is designed to adaptively highlight informative channel-wise features. Experiments show that the proposed DBWT-AFNet outperforms the state-of- the-art methods, especially for ECG segments classification across different subjects, where no data from testing subjects have been used in training.

Vigilance decrement in driving tasks has been reported to be a major factor in fatal accidents and could severely endanger public transportation safety. However, efficient approaches for estimating vigilance in real driving environment are still lacking. In this paper, we propose a novel approach for implementing continuous vigilance estimation using forehead electrooculograms (EOGs) acquired by wearable dry electrodes in both simulated and real driving environments. To improve the feasibility of this approach for real-world applications, a forehead EOG-based electrode placement with only four electrodes is designed. Flexible dry electrodes and an acquisition board are integrated as a wearable device for recording EOGs. Twenty and ten subjects participated in the simulated and real-world driving environment experiments, respectively. Accurate eye movement parameters from eye-tracking glasses are extracted to calculate the PERCLOS index for vigilance annotation. This is because the vigilance state is a temporally dynamic process, and a continuous conditional random field and a continuous conditional neural field are introduced to construct more accurate vigilance estimation models. To evaluate the efficiency of our system, systematic experiments are performed in real scenarios under various illumination and weather conditions following laboratory simulations as preliminary studies. The experimental results demonstrate that the wearable dry electrode prototype, which has a relatively comfortable forehead setup, can efficiently capture vigilance dynamics. The best mean correlation coefficients achieved by our proposed approach are 71.18% and 66.20% in laboratory simulations and real-world driving environments, respectively. The cross-environment experiments are performed to evaluate the simulated-to-real generalization and a best mean correlation coefficient of 53.96% is achieved.

In this demonstration, we present a non-invasive, real-time lung imaging system based on the electrical impedance tomography (EIT) technique. EIT is a medical imaging technique based on the electrical properties, i.e. resistivity and permittivity of tissues and organs. This demo is based on an EIT system-on-chip that utilizes frequency division multiplexing scheme to improve the throughput by 10, allowing clinicians to identify and prevent mechanical pulmonary injury during lung ventilation.

A CMOS mixer with wideband input impedance matching and high conversion gain is presented in this paper. Dual RLC circuits are utilized with Gilbert mixer for wideband input matching. Capacitive feedback, and inductive series and shunt peaking techniques, are used to implement the RF port matching network. Inductive peaking is also adopted to widen the 3-dB conversion gain bandwidth. Active load with AC resistive blocking is employed to boost the mixer conversion gain. The proposed circuit is designed, simulated and implemented in XFAB XH018 process with VDD of 1.8V. It achieves a very good RF matching over a band of 5.6–14.6GHz, with a conversion gain of 25.0–28.2dB over the desired band of frequency.

In recent years, action recognition has been widely explored and attains significant performance improvement. In this paper, we propose a real-time action recognition specified convolutional 3D (AR-C3D) neural network for human-computer interaction. The CNN structure is optimized to decrease the complexity. Furthermore, Winograd algorithm is adopted to accelerate computation. It achieves 89.9% accuracy in the application which refers to the robot classifies the video captured by itself and would either imitate human's action or give verbal feedback. The Artix-7 FPGA implementation result outperforms previous work in terms of resource utilization and no external storage is consumed. One video can be processed in 6.6ms, and the power consumption is only 2.7W.

This paper presents an untrimmed stable CMOS Nano-Ampere current reference over a wide temperature range with curvature-compensation scheme which is realized by utility self-biased CMOS β-multiplier circuit and operating near to zero-temperature coefficient of MOSFET. Besides, analysis of the proposed circuit is illustrated. The current reference is 142.5 nA with temperature coefficient (TC) of 40 ppm/ °C over a temperature range from -40 °C to 85 °C and the line sensitivity is 1.45%/V in a range of supply voltage from 1.2 V to 2 V. The proposed current reference consumes a silicon area of 0.02 mm2and simulation results of the post-layout reveal that the current reference and the TC are deviated by 0.2 nA and 0.69 ppm/°C, respectively. The proposed circuit is designed and taped-out in 0.18 μm CMOS technology with single supply voltage of 1.8 V.

This paper presents a batteryless DC-DC boost converter for thermoelectric energy harvesting application. With a stepping-up architecture and by inductor sharing, only one off-chip inductor is employed. Fabricated in 0.18μm CMOS process, the chip can be cold-started at 190mV and sustain operation with a minimum input voltage of 50mV. Zero-current switching (ZCS) and maximum power point tracking (MPPT) techniques are utilized to enhance the measured peak efficiency to 60%. And the output voltage can be regulated from 1V to 1.6V.

Telemedicine provides health care services at a distance using information and communication technologies, which intends to be a solution to the challenges faced by current health care systems with growing numbers of population, increased demands from patients, and shortages in human resources. Recent advances in telemedicine, especially in wearable electrocardiogram (ECG) monitors, call for more intelligent and efficient automatic ECG analysis and diagnostic systems. We present a streaming architecture implemented on Field-Programmable Gate Arrays (FPGAs) to accelerate real-time ECG signal analysis and diagnosis in a pipelining and parallel way. Association-rule mining is employed to generate early diagnostic results by matching features of ECG with generated association rules. To improve performance of the processing, we propose a hardware-oriented data-mining algorithm named Bit_Q_Apriori . The corresponding hardware implementation indicates a good scalability and outperforms other hardware designs in terms of performance, throughput, and hardware cost.

Biomedical implanted electronic devices utilize inductively coupled coils for power and data transmission. To achieve efficient power transmission and high data rate, a dual band telemetry system has been proposed where different carrier frequencies can be used for power and data transmission, respectively. In this system, the physical parameters and geometrical structure of the coils must be carefully optimized to avoid the strong power interference to data transmission, which diminishes the advantages of multiple carrier frequencies. In this demonstration, an optimization procedure is introduced about the optimization of two pairs of coils based on an overlapping structure which minimizes power-to-signal interference in the data transmission. We applied the optimization procedure to a practical design case, and the results showed that our optimization procedure can achieve both optimal power transmission efficiency and high signal to interference ratio.

This paper serves as an introduction to visual prostheses. Visual prostheses have attracted a lot of attention in recent years. With the potential of helping the blind to regain or improve their vision, researchers have been trying to tap into the visual pathways using their novel circuits and systems and interact with the brain through electronic ways. Having already benefited a lot from recent advances in electronics, MEMS, materials, and other sciences and technologies, and having already achieved a lot in the past, research in this field still prompt researchers to go beyond what current technologies can offer. In particular, this paper will review the challenges associated with circuit design for the visual prostheses, for example, the high-voltage compliant circuits, high-density drivers, power management schemes, and efficient stimulation.

Patients suffering from facial paralysis are on the hazard of disfigurement and loss of vision due to loss of blink function. Functional-electrical stimulation (FES) is one possible way of restoring blink and other functions in these patients. A blink restoration system for uni-lateral facial paralyzed patients is described in this paper. The system achieves restoration of synchronized blink through processing on EMG signal from eyelid of healthy side in real-time and stimulating the paralyzed eyelid. Design issues are discussed, including real-time artifact blanking, stimulating strategies and EMG processing. An artifact removal algorithm based on software sample and hold technique is proposed. Finally, the whole system has been verified on rabbits.

In this paper, a novel overlapping coil structure for dual band power and data telemetry systems is proposed. Through carefully choosing the coil structural parameters, overlapping structure can achieve both low power interference and ease of manufacturing at the same time. Two design examples are presented and analyzed. Compared with conventional structures which set coils on the same plane, the overlapping structure shows higher power interference rejection and better overall signal quality.