This paper presents a low-dropout regulator (LDO) with a 5-A current capability, supporting a wide range of output capacitors. An output impedance shaping technique is proposed, introducing two half-zeros into the loop to shape the LDO’s output impedance between resistive and inductive characteristics. The proposed technique ensures a decent frequency and transient response across an output capacitance range from 0 to 150 μF. To achieve a widely adjustable output voltage, a two-stage buffer with fast transient response and active feedback is employed, which further improves the overall stability and transient performance of the LDO. Under light-load conditions, the current sensing module provides an auxiliary feedback path for the error amplifier (EA), thereby securing loop stability by pushing the dominant pole to a higher frequency and lowering the DC loop gain. Implemented with a 0.18 μm CMOS process, the chip occupies an area of 1.9 × 1.9 mm2. The LDO regulates an output voltage from 0.8 to 3.5 V within an input voltage range of 2.8 to 5.5 V. With a minimum dropout voltage of 150 mV, the open-loop gain is 80 dB and remains comparatively unaffected by load alterations, ensuring a robust load regulation of 1.3 mV/A. Measured results demonstrate a 170-mV undershoot during a 5-A/1-μs load step without external output capacitors.

This paper describes a temperature sensor with a 16-bit Zoom Analog-to-Digital (ADC) intended for Internet-of-Things (IoT). It uses a BJT-based front-end to generate a proportion related to temperature, relying on the PTAT and CTAT properties. Noise cancellation technique and dynamic element matching (DEM) are used to decrease the effect of non-ideal factors while a guard-band method is proposed to improve the conversion accuracy of Zoom ADC. The prototype sensor is fabricated in a 55nm CMOS process and occupies a core area of 0.083 mm2. The sensor achieves an inaccuracy of only 0.28 °C (3σ) from −40°C to 125°C with the help of the improved 1-point calibration. Operating at 1.2V supply, it consumes 9.9μW and obtains a resolution of 10mk in a 10.68ms conversion time, showing a figure-of-merit (FOM) of 10.61 pJ·K2.

This paper proposes a BJT-based temperature sensor with a 16-bit SAR ADC fabricated in a standard 55-nm CMOS process. Errors resulting from the front end are reduced by using chopping, dynamic element matching, and PTAT circuit compensation. It obtains a resolution of 0.04 °C and a resolution figure of merit (FoM) of$5.12\ \text{pJ}\cdot \mathrm{K}^{2}$with the utilization of a 16-bit SAR ADC. The sensor takes 0.1 ms to complete a round of conversion. The switched-capacitor amplifier is applied to scale up the input range of the SAR ADC and improve the effective dynamic range. The sensor achieves an accuracy of ± 0.6 °C from −40 °C to 125 °C. It occupies an area of 0.234 mm2and draws a current of$6.4\ \mu\mathrm{A}$(analog front end) from a 1.2-V supply voltage.

This paper proposes the theoretical analyses, design method, design process and design results of a high power bidirectional 48V-12V DCDC converter system in electric vehicle (EV) application. The design is divided into 3 levels that are topology level, control method level, and block level based on IC with 3 steps respectively. In topology level, full-bridge CLLC is chosen for its high efficiency and good stability. 8 stages are designed for full-bridge CLLC in one switching period. Topology design mainly focuses on determining resonant components by inherent frequency and quality factor. In control method level, FPD (Frequency, Phase shift, and Duty) influence the performance of the whole system in their own way and FPD control method is chosen for this system. In block level, a main control loop that consists of 3 interlaced loops is illustrated by functional blocks and achieved actually by IC design. The whole design is verified by analog IC simulation whose results confirm the basic function and expected performance of the system. The output voltage accuracy enters 0.1% range and efficiency is up to 99.15% in buck mode with full load. The performances of the converter system in other conditions are also competitive.

This paper presents a complete digital pulse-width modulation (PWM) controller for MHz active clamp flyback (ACF) converter with gallium nitride (GaN) devices. A proposed model based on state-space averaging is used to predict the dynamic behavior of ACF converter. With the model, a digital PID compensator is introduced to achieve high-speed dynamic response. Meanwhile, a high-resolution digital pulse-width modulator is employed to meet the requirement of tight output voltage regulation. The implementation techniques are experimentally verified on a 45 W (20 V/2.25 A) prototype of ACF converter based on FPGA. The proposed digital control scheme enables the system operates at the switching frequency of 1 MHz and obtains less than 200 us recovery time in case of load transient (2-0.2 A). The AC-DC adapter's prototype can achieve the maximum efficiency of 91.34% and power density (exclude case) of 18 W/in3.

GaN-based Adaptive-On-Time (AOT) V2buck converter is getting more attention for the applications as data center power supply because of its fast transient response and high efficiency. However, in high-frequency and high step-down Buck converters, the frequency deviation and the dead time power loss become serious problems. In this paper, a GaN-based AOT V2buck converter that adopts a high-accuracy on-time generator and successive feedback regulation with capacitive-scaling dead time control is presented. Designed by using CSMC high voltage 0.25 um process, the controller IC can enable a 100 W (5 V/20 A) buck converter to operate at power switch frequency of 2 MHz and adaptively adjust the dead time under various conditions. With the proposed on-time and dead time control, the frequency variation is only 4% and reverse conduction length of GaN devices is less than 2 ns. The input range of this converter is from 12 V to 60 V and the peak efficiency is 90% at 48 V typical input.

The Active Clamp Flyback (ACF) converter utilizing Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) is expected to achieve high switching frequency and high efficiency for system miniaturization in AC-DC adapter applications. Due to high switching speed and large reverse conduction loss of GaN devices, the improper dead time length in a high-frequency ACF converter can lead to severe oscillation and efficiency decrease. This paper presents a high-frequency and high-efficiency ACF converter with an adaptive dual edge dead time modulation which can realize ideal Zero Voltage Switching (ZVS) ON for primary GaN FETs and Zero Current Switching (ZCS) for GaN synchronous rectifier. Designed by a high voltage 0.18um BCD process, the controller IC can enable a 65 W (19.5V/3.3A) ACF converter to operate at 1 MHz and automatically adjust the dead-time length under universal input (100VAC-260VAC) as well as wide load condition (0.33A-3.33A). With the proposed adaptive dual edge dead time control, the ACF converter can achieve the maximum efficiency of 94.3% and around 80% efficiency at the worst case. In addition, the converter based on this analog IC solution excludes any external active sampling devices, which will bring lower system cost.

This paper presents a high-frequency half-bridge driver for GaN HEMTs with bandgap reference comparator clamping (BGRCC). Due to the characteristics of GaN HEMTs, the high-side supply voltage must be clamped to prevent it from exceeding the voltage limits in half-bridge configuration. The BGRCC scheme is simple and effective with low power consumption, which can adaptively keep the high-side supply voltage at an appropriate level. And the drive circuit for GaN HEMTs is specially designed and optimized to acquire low propagation delay as well as excellent mismatching delay. The simulation results show that the BGRCC scheme can clamp the high-side supply voltage at an average of 5.37 V with acceptable ripples and the maximum propagation delay for the drive circuit is around 22.6 ns when the switching frequency varies from 1 MHz to 10 MHz.

A novel kind of chip which is used in high precision and low cost arc detection circuit (leakage detection included) was designed. Based on CSMC's 0.5pm process, the pad is specially designed to produce a specific capacitor. Cascode current mirror and trimming capacitors are used to generate a precise timing signal. High speed, large bandwidth and low offset op-amps with rail to rail output stage are used to realize the function of precise amplification of the current information. The chip is designed and simulated on the platform of Cadence. The experimental result shows that the chip can detect arc which is wider than 150ns and generate the corresponding interrupt signal.

A novel data processing circuit in high-speed serial communication has been demonstrated in this work. The circuit, including a serializer and a frequency divider, was developed to convert the transmission signals into the desired format. The chip design is based on TSMC 0.25μm mixed signal model, and semi-custom design methodology is used. Pre- and post-layout simulation results indicated that the speed of circuit has reached 480MHz. Moreover, the data are processed properly in agreement with USB2.0 specification.