EDBT 2026 Demo / reviewers in the wild / expert
Ming-Fu Tsai
dblp:10/6408
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 2002
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 80% Memory systems · 20% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test › design for testability
built-in self-test |
0.0 | 1 | 2002 | Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 2002 | Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002 |
Electronic design automation › hardware verification and test › memory testing
march test algorithm |
0.0 | 1 | 2002 | Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002 |
Electronic design automation › hardware verification and test
memory testing |
0.0 | 1 | 2002 | Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002 |
Memory systems
random-access memory |
0.0 | 1 | 2002 | Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002 |
Methods — techniques the papers use, named apart from their topics
multiple data backgrounds · 0.0march-based testing · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2002 | Neighborhood pattern-sensitive fault testing and diagnostics for random-access memoriesabstractThe authors present test algorithms for go/no-go and diagnostic test of memories, covering neighborhood pattern-sensitive faults (NPSFs). The proposed test algorithms are March based, which have linear time complexity and result in a simple built-in self-test (BIST) implementation. Although conventional March algorithms do not generate all neighborhood patterns to test the NPSFs, they can be modified by using multiple data backgrounds such that all neighborhood patterns can be generated. The proposed multibackground March algorithms have shorter test lengths than previously reported ones, and the diagnostic test algorithm guarantees 100% diagnostic resolution for NPSFs and conventional RAM faults. Based on the proposed algorithms, the authors also present a cost-effective BIST design. The BIST circuit is programmable, and it supports March algorithms, including the proposed multibackground one. Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 2001 | Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor MemoriesabstractWe present two memory test algorithms for neighborhood pattern sensitive faults (NPSFs), including static NPSF (SNPSF), passive NPSF (PNPSF) and active NPSF (ANPSF). March algorithms are widely used in memory testing because of their linear time complexity and ease in built-in self-test (BIST) implementation. Although conventional March algorithms do not generate all neighborhood patterns for testing the NPSFs, they can be modified by using multiple data backgrounds such that all neighborhood patterns can be generated. The proposed multi-background March algorithms have shorter test length than previously proposed ones (68N for detecting SNPSFs and PNPSFs and 96N for detecting all NPSFs). Also, based on the proposed algorithms, linear-time BIST circuit can be implemented with low area overhead. Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu |
VTS | 2 |